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Searched refs:R (Results 1 – 25 of 107) sorted by relevance

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/drivers/staging/skein/
Dskein_block.c125 #define I256(R) \ in skein_256_process_block() argument
128 X0 += ks[((R)+1) % 5]; \ in skein_256_process_block()
129 X1 += ks[((R)+2) % 5] + ts[((R)+1) % 3]; \ in skein_256_process_block()
130 X2 += ks[((R)+3) % 5] + ts[((R)+2) % 3]; \ in skein_256_process_block()
131 X3 += ks[((R)+4) % 5] + (R)+1; \ in skein_256_process_block()
141 #define I256(R) \ in skein_256_process_block() argument
144 X0 += ks[r+(R)+0]; \ in skein_256_process_block()
145 X1 += ks[r+(R)+1] + ts[r+(R)+0]; \ in skein_256_process_block()
146 X2 += ks[r+(R)+2] + ts[r+(R)+1]; \ in skein_256_process_block()
147 X3 += ks[r+(R)+3] + r+(R); \ in skein_256_process_block()
[all …]
/drivers/hwmon/pmbus/
Dlm25066.c61 short m, b, R; member
71 .R = -2,
75 .R = -2,
79 .R = -2,
83 .R = -3,
87 .R = -4,
92 .R = -2,
98 .R = -2,
102 .R = -2,
106 .R = -2,
[all …]
Dmax34440.c213 .R[PSC_VOLTAGE_IN] = 3, /* R = 0 in datasheet reflects mV */
216 .R[PSC_VOLTAGE_OUT] = 3, /* R = 0 in datasheet reflects mV */
219 .R[PSC_CURRENT_OUT] = 3, /* R = 0 in datasheet reflects mA */
222 .R[PSC_TEMPERATURE] = 2,
256 .R[PSC_VOLTAGE_IN] = 3,
259 .R[PSC_VOLTAGE_OUT] = 3,
262 .R[PSC_CURRENT_OUT] = 3,
265 .R[PSC_TEMPERATURE] = 2,
268 .R[PSC_FAN] = 0,
299 .R[PSC_VOLTAGE_IN] = 3,
[all …]
Dadm1275.c295 info->R[PSC_CURRENT_OUT] = -1; in adm1275_probe()
305 info->R[PSC_VOLTAGE_IN] = -1; in adm1275_probe()
308 info->R[PSC_VOLTAGE_OUT] = -1; in adm1275_probe()
312 info->R[PSC_VOLTAGE_IN] = -2; in adm1275_probe()
315 info->R[PSC_VOLTAGE_OUT] = -2; in adm1275_probe()
319 info->R[PSC_VOLTAGE_IN] = -1; in adm1275_probe()
322 info->R[PSC_VOLTAGE_OUT] = -1; in adm1275_probe()
332 info->R[PSC_POWER] = -1; in adm1275_probe()
372 info->R[PSC_POWER] = -2; in adm1275_probe()
376 info->R[PSC_POWER] = -1; in adm1275_probe()
/drivers/media/platform/s5p-mfc/
Ds5p_mfc_opr_v6.c2051 #define R(m, r) mfc_regs.m = S5P_MFC_REG_ADDR(dev, r) in s5p_mfc_init_regs_v6_plus() macro
2053 R(risc_on, S5P_FIMV_RISC_ON_V6); in s5p_mfc_init_regs_v6_plus()
2054 R(risc2host_int, S5P_FIMV_RISC2HOST_INT_V6); in s5p_mfc_init_regs_v6_plus()
2055 R(host2risc_int, S5P_FIMV_HOST2RISC_INT_V6); in s5p_mfc_init_regs_v6_plus()
2056 R(risc_base_address, S5P_FIMV_RISC_BASE_ADDRESS_V6); in s5p_mfc_init_regs_v6_plus()
2057 R(mfc_reset, S5P_FIMV_MFC_RESET_V6); in s5p_mfc_init_regs_v6_plus()
2058 R(host2risc_command, S5P_FIMV_HOST2RISC_CMD_V6); in s5p_mfc_init_regs_v6_plus()
2059 R(risc2host_command, S5P_FIMV_RISC2HOST_CMD_V6); in s5p_mfc_init_regs_v6_plus()
2060 R(firmware_version, S5P_FIMV_FW_VERSION_V6); in s5p_mfc_init_regs_v6_plus()
2061 R(instance_id, S5P_FIMV_INSTANCE_ID_V6); in s5p_mfc_init_regs_v6_plus()
[all …]
/drivers/net/ethernet/intel/ixgb/
Dixgb.h126 #define IXGB_DESC_UNUSED(R) \ argument
127 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
128 (R)->next_to_clean - (R)->next_to_use - 1)
130 #define IXGB_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i])) argument
131 #define IXGB_RX_DESC(R, i) IXGB_GET_DESC(R, i, ixgb_rx_desc) argument
132 #define IXGB_TX_DESC(R, i) IXGB_GET_DESC(R, i, ixgb_tx_desc) argument
133 #define IXGB_CONTEXT_DESC(R, i) IXGB_GET_DESC(R, i, ixgb_context_desc) argument
/drivers/staging/vt6655/
Dmichael.c57 static u32 L, R; /* Current state */ variable
69 R = K1; in s_vClear()
91 R ^= ROL32(L, 17); in s_vAppendByte()
92 L += R; in s_vAppendByte()
93 R ^= ((L & 0xff00ff00) >> 8) | ((L & 0x00ff00ff) << 8); in s_vAppendByte()
94 L += R; in s_vAppendByte()
95 R ^= ROL32(L, 3); in s_vAppendByte()
96 L += R; in s_vAppendByte()
97 R ^= ROR32(L, 2); in s_vAppendByte()
98 L += R; in s_vAppendByte()
[all …]
/drivers/net/ethernet/intel/i40evf/
Di40evf.h97 #define I40E_RX_DESC(R, i) (&(((union i40e_32byte_rx_desc *)((R)->desc))[i])) argument
98 #define I40E_TX_DESC(R, i) (&(((struct i40e_tx_desc *)((R)->desc))[i])) argument
99 #define I40E_TX_CTXTDESC(R, i) \ argument
100 (&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
129 #define I40EVF_DESC_UNUSED(R) \ argument
130 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
131 (R)->next_to_clean - (R)->next_to_use - 1)
133 #define I40EVF_RX_DESC_ADV(R, i) \ argument
134 (&(((union i40e_adv_rx_desc *)((R).desc))[i]))
135 #define I40EVF_TX_DESC_ADV(R, i) \ argument
[all …]
Di40e_adminq.h33 #define I40E_ADMINQ_DESC(R, i) \ argument
34 (&(((struct i40e_aq_desc *)((R).desc_buf.va))[i]))
73 #define I40E_ADMINQ_DETAILS(R, i) \ argument
74 (&(((struct i40e_asq_cmd_details *)((R).cmd_buf.va))[i]))
/drivers/net/ethernet/intel/e1000/
De1000.h215 #define E1000_DESC_UNUSED(R) \ argument
216 ((((R)->next_to_clean > (R)->next_to_use) \
217 ? 0 : (R)->count) + (R)->next_to_clean - (R)->next_to_use - 1)
219 #define E1000_RX_DESC_EXT(R, i) \ argument
220 (&(((union e1000_rx_desc_extended *)((R).desc))[i]))
221 #define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i])) argument
222 #define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc) argument
223 #define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc) argument
224 #define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc) argument
/drivers/video/fbdev/kyro/
DSTG4000InitDevice.c121 u32 R = 0, F = 0, OD = 0, ODIndex = 0; in ProgramClock() local
145 R = STG4K3_PLL_MIN_R; in ProgramClock()
148 while (R <= STG4K3_PLL_MAX_R) { in ProgramClock()
150 ulTmp = R * (ulScaleClockReq << OD); in ProgramClock()
168 ulVCO = refClock / R; in ProgramClock()
186 …ulPhaseScore = (((refClock / R) - (refClock / STG4K3_PLL_MAX_R))) / ((refClock - (refClock / STG4K… in ProgramClock()
195 ulBestR = R; in ProgramClock()
212 ulBestR = R; in ProgramClock()
221 R++; in ProgramClock()
245 u32 F, R, P; in SetCoreClockPLL() local
[all …]
/drivers/net/ethernet/intel/i40e/
Di40e_fcoe.h31 #define I40E_DDP_CONTEXT_DESC(R, i) \ argument
32 (&(((struct i40e_fcoe_ddp_context_desc *)((R)->desc))[i]))
34 #define I40E_QUEUE_CONTEXT_DESC(R, i) \ argument
35 (&(((struct i40e_fcoe_queue_context_desc *)((R)->desc))[i]))
37 #define I40E_FILTER_CONTEXT_DESC(R, i) \ argument
38 (&(((struct i40e_fcoe_filter_context_desc *)((R)->desc))[i]))
Di40e_adminq.h33 #define I40E_ADMINQ_DESC(R, i) \ argument
34 (&(((struct i40e_aq_desc *)((R).desc_buf.va))[i]))
73 #define I40E_ADMINQ_DETAILS(R, i) \ argument
74 (&(((struct i40e_asq_cmd_details *)((R).cmd_buf.va))[i]))
/drivers/tty/
Drocket_int.h356 Byte_t R[RREGDATASIZE]; member
494 (ChP)->R[0x0e] = 0x86; \
495 out32((ChP)->IndexAddr,&(ChP)->R[0x0c]); \
533 (ChP)->R[0x32] = 0x0a; \
534 out32((ChP)->IndexAddr,&(ChP)->R[0x30]); \
572 (ChP)->R[0x06] = 0x8a; \
573 out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \
609 (ChP)->R[0x0e] = 0x21; \
610 out32((ChP)->IndexAddr,&(ChP)->R[0x0c]); \
656 (ChP)->R[0x32] = 0x08; \
[all …]
/drivers/net/ethernet/intel/
DKconfig21 tristate "Intel(R) PRO/100+ support"
25 This driver supports Intel(R) PRO/100 family of adapters.
47 tristate "Intel(R) PRO/1000 Gigabit Ethernet support"
50 This driver supports Intel(R) PRO/1000 gigabit ethernet family of
68 tristate "Intel(R) PRO/1000 PCI-Express Gigabit Ethernet support"
73 This driver supports the PCI-Express Intel(R) PRO/1000 gigabit
89 tristate "Intel(R) 82575/82576 PCI-Express Gigabit Ethernet support"
95 This driver supports Intel(R) 82575/82576 gigabit ethernet family of
113 bool "Intel(R) PCI-Express Gigabit adapters HWMON support"
133 tristate "Intel(R) 82576 Virtual Function Ethernet support"
[all …]
/drivers/gpu/drm/rcar-du/
DKconfig2 tristate "DRM Support for R-Car Display Unit"
11 Choose this option if you have an R-Car chipset.
15 bool "R-Car DU LVDS Encoder Support"
19 Enable support the R-Car Display Unit embedded LVDS encoders
/drivers/net/ethernet/intel/igbvf/
Digbvf.h299 #define IGBVF_RX_DESC_ADV(R, i) \ argument
300 (&((((R).desc))[i].rx_desc))
301 #define IGBVF_TX_DESC_ADV(R, i) \ argument
302 (&((((R).desc))[i].tx_desc))
303 #define IGBVF_TX_CTXTDESC_ADV(R, i) \ argument
304 (&((((R).desc))[i].tx_context_desc))
/drivers/gpu/drm/i915/
Di915_cmd_parser.c109 #define R CMD_DESC_REJECT macro
118 CMD( MI_USER_INTERRUPT, SMI, F, 1, R ),
123 CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ),
124 CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ),
146 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
149 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
150 CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ),
158 CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ),
210 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),
211 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, R ),
[all …]
/drivers/media/dvb-frontends/
Dmb86a16.c479 unsigned char R) in rf_val_set() argument
525 M = f * (1 << R) / 2; in rf_val_set()
528 rf_val[1] = (R << 5) | ((M & 0x1f000) >> 12); in rf_val_set()
664 int R, M, fOSC, fOSC_OFS; in freqerr_chk() local
715 R = (temp1 & 0xe0) >> 5; in freqerr_chk()
717 if (R == 0) in freqerr_chk()
741 unsigned char R; in vco_dev_get() local
744 R = 0; in vco_dev_get()
746 R = 1; in vco_dev_get()
748 return R; in vco_dev_get()
[all …]
Dcx24113.c307 u8 R, r; in cx24113_calc_pll_nf() local
331 R = 0; in cx24113_calc_pll_nf()
333 R = cx24113_set_ref_div(state, R + 1); in cx24113_calc_pll_nf()
336 N = (freq_hz / 100 * vcodiv) * R; in cx24113_calc_pll_nf()
341 } while (N < 6 && R < 3); in cx24113_calc_pll_nf()
348 F *= (u64) (R * vcodiv * 262144); in cx24113_calc_pll_nf()
349 dprintk("1 N: %d, F: %lld, R: %d\n", N, (long long)F, R); in cx24113_calc_pll_nf()
354 dprintk("2 N: %d, F: %lld, R: %d\n", N, (long long)F, R); in cx24113_calc_pll_nf()
357 dprintk("3 N: %d, F: %lld, R: %d\n", N, (long long)F, R); in cx24113_calc_pll_nf()
370 dprintk("4 N: %d, F: %lld, R: %d\n", N, (long long)F, R); in cx24113_calc_pll_nf()
/drivers/net/ethernet/intel/e1000e/
De1000.h446 #define E1000_RX_DESC_PS(R, i) \ argument
447 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
448 #define E1000_RX_DESC_EXT(R, i) \ argument
449 (&(((union e1000_rx_desc_extended *)((R).desc))[i]))
450 #define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i])) argument
451 #define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc) argument
452 #define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc) argument
/drivers/dma/sh/
DKconfig45 tristate "Renesas R-Car HPB DMAC support"
48 Enable support for the Renesas R-Car series DMA controllers.
51 tristate "Renesas R-Car Audio DMAC Peripheral Peripheral support"
54 Enable support for the Renesas R-Car Audio DMAC Peripheral Peripheral controllers.
/drivers/net/wireless/ath/wil6210/
Dfw.c27 #define R(a) ioread32(wil->csr + HOSTADDR(a)) macro
31 #define S(a, v) W(a, R(a) | v)
33 #define C(a, v) W(a, R(a) & ~v)
/drivers/net/ethernet/atheros/atl1c/
Datl1c.h103 #define ATL1C_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i])) argument
104 #define ATL1C_RFD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_rx_free_desc) argument
105 #define ATL1C_TPD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_tpd_desc) argument
106 #define ATL1C_RRD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_recv_ret_status) argument
/drivers/crypto/qat/
DKconfig14 tristate "Support for Intel(R) DH895xCC"
19 Support for Intel(R) DH895xcc with Intel(R) QuickAssist Technology

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