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Searched refs:RING_SPACE (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/nouveau/
Dnvc0_fbcon.c37 ret = RING_SPACE(chan, rect->rop == ROP_COPY ? 7 : 11); in nvc0_fbcon_fillrect()
72 ret = RING_SPACE(chan, 12); in nvc0_fbcon_copyarea()
106 ret = RING_SPACE(chan, 11); in nvc0_fbcon_imageblit()
132 ret = RING_SPACE(chan, push + 1); in nvc0_fbcon_imageblit()
189 ret = RING_SPACE(chan, 60); in nvc0_fbcon_accel_init()
Dnv50_fbcon.c37 ret = RING_SPACE(chan, rect->rop == ROP_COPY ? 7 : 11); in nv50_fbcon_fillrect()
72 ret = RING_SPACE(chan, 12); in nv50_fbcon_copyarea()
106 ret = RING_SPACE(chan, 11); in nv50_fbcon_imageblit()
132 ret = RING_SPACE(chan, push + 1); in nv50_fbcon_imageblit()
189 ret = RING_SPACE(chan, 59); in nv50_fbcon_accel_init()
Dnv04_fbcon.c37 ret = RING_SPACE(chan, 4); in nv04_fbcon_copyarea()
57 ret = RING_SPACE(chan, 7); in nv04_fbcon_fillrect()
91 ret = RING_SPACE(chan, 8); in nv04_fbcon_imageblit()
118 ret = RING_SPACE(chan, iter_len + 1); in nv04_fbcon_imageblit()
203 if (RING_SPACE(chan, 49)) { in nv04_fbcon_accel_init()
Dnvc0_fence.c34 int ret = RING_SPACE(chan, 6); in nvc0_fence_emit32()
50 int ret = RING_SPACE(chan, 5); in nvc0_fence_sync32()
Dnouveau_bo.c576 int ret = RING_SPACE(chan, 2); in nve0_bo_move_init()
590 int ret = RING_SPACE(chan, 10); in nve0_bo_move_copy()
609 int ret = RING_SPACE(chan, 2); in nvc0_bo_move_init()
631 ret = RING_SPACE(chan, 11); in nvc0_bo_move_copy()
669 ret = RING_SPACE(chan, 12); in nvc0_bo_move_m2mf()
708 ret = RING_SPACE(chan, 11); in nva3_bo_move_copy()
737 int ret = RING_SPACE(chan, 7); in nv98_bo_move_exec()
755 int ret = RING_SPACE(chan, 7); in nv84_bo_move_exec()
771 int ret = RING_SPACE(chan, 6); in nv50_bo_move_init()
799 ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled)); in nv50_bo_move_m2mf()
[all …]
Dnv17_fence.c50 ret = RING_SPACE(prev, 5); in nv17_fence_sync()
60 if (!ret && !(ret = RING_SPACE(chan, 5))) { in nv17_fence_sync()
Dnv84_fence.c41 int ret = RING_SPACE(chan, 8); in nv84_fence_emit32()
59 int ret = RING_SPACE(chan, 7); in nv84_fence_sync32()
Dnv04_fence.c41 int ret = RING_SPACE(chan, 2); in nv04_fence_emit()
Dnv10_fence.c33 int ret = RING_SPACE(chan, 2); in nv10_fence_emit()
Dnouveau_dma.h89 RING_SPACE(struct nouveau_channel *chan, int size) in RING_SPACE() function
Dnouveau_chan.c362 ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS); in nouveau_channel_init()
380 ret = RING_SPACE(chan, 2); in nouveau_channel_init()
Dnouveau_display.c665 ret = RING_SPACE(chan, 2); in nouveau_page_flip_emit()
757 ret = RING_SPACE(chan, 8); in nouveau_crtc_page_flip()
Dnouveau_gem.c745 ret = RING_SPACE(chan, req->nr_push * 2); in nouveau_gem_ioctl_pushbuf()
759 ret = RING_SPACE(chan, req->nr_push * (2 + NOUVEAU_DMA_SKIPS)); in nouveau_gem_ioctl_pushbuf()
Dnv50_display.c534 ret = RING_SPACE(chan, 8); in nv50_display_flip_next()
549 ret = RING_SPACE(chan, 12); in nv50_display_flip_next()
568 ret = RING_SPACE(chan, 10); in nv50_display_flip_next()
Dnouveau_drm.c234 ret = RING_SPACE(drm->channel, 2); in nouveau_accel_init()