Searched refs:RREG32_PCIE (Results 1 – 5 of 5) sorted by relevance
64 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_tlb_flush()66 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_tlb_flush()150 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_enable()170 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_disable()511 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()527 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()529 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()545 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_get_pcie_lanes()572 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_debugfs_pcie_gart_info()574 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); in rv370_debugfs_pcie_gart_info()[all …]
5516 orig = data = RREG32_PCIE(PCIE_CNTL2); in si_enable_bif_mgls()7261 tmp = RREG32_PCIE(PCIE_LC_STATUS1); in si_pcie_gen3_enable()7376 orig = data = RREG32_PCIE(PCIE_P_CNTL); in si_program_aspm()7539 orig = data = RREG32_PCIE(PCIE_CNTL2); in si_program_aspm()7547 data = RREG32_PCIE(PCIE_LC_STATUS1); in si_program_aspm()
131 tmp = RREG32_PCIE(PCIE_P_CNTL); in rv6xx_enable_pll_sleep_in_l1()
122 tmp = RREG32_PCIE(PCIE_P_CNTL); in rv770_enable_pll_sleep_in_l1()
2495 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) macro