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Searched refs:RegAddr (Results 1 – 12 of 12) sorted by relevance

/drivers/staging/rtl8723au/hal/
Dodm_interface.c27 u32 RegAddr in ODM_Read1Byte() argument
32 return rtl8723au_read8(Adapter, RegAddr); in ODM_Read1Byte()
35 u16 ODM_Read2Byte(struct dm_odm_t *pDM_Odm, u32 RegAddr) in ODM_Read2Byte() argument
39 return rtl8723au_read16(Adapter, RegAddr); in ODM_Read2Byte()
42 u32 ODM_Read4Byte(struct dm_odm_t *pDM_Odm, u32 RegAddr) in ODM_Read4Byte() argument
46 return rtl8723au_read32(Adapter, RegAddr); in ODM_Read4Byte()
49 void ODM_Write1Byte(struct dm_odm_t *pDM_Odm, u32 RegAddr, u8 Data) in ODM_Write1Byte() argument
53 rtl8723au_write8(Adapter, RegAddr, Data); in ODM_Write1Byte()
56 void ODM_Write2Byte(struct dm_odm_t *pDM_Odm, u32 RegAddr, u16 Data) in ODM_Write2Byte() argument
60 rtl8723au_write16(Adapter, RegAddr, Data); in ODM_Write2Byte()
[all …]
Drtl8723a_phycfg.c87 PHY_QueryBBReg(struct rtw_adapter *Adapter, u32 RegAddr, u32 BitMask) in PHY_QueryBBReg() argument
91 OriginalValue = rtl8723au_read32(Adapter, RegAddr); in PHY_QueryBBReg()
120 PHY_SetBBReg(struct rtw_adapter *Adapter, u32 RegAddr, u32 BitMask, u32 Data) in PHY_SetBBReg() argument
127 OriginalValue = rtl8723au_read32(Adapter, RegAddr); in PHY_SetBBReg()
132 rtl8723au_write32(Adapter, RegAddr, Data); in PHY_SetBBReg()
348 u32 RegAddr, u32 BitMask) in PHY_QueryRFReg() argument
355 Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr); in PHY_QueryRFReg()
385 u32 RegAddr, u32 BitMask, u32 Data) in PHY_SetRFReg() argument
393 Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr); in PHY_SetRFReg()
398 phy_RFSerialWrite(Adapter, eRFPath, RegAddr, Data); in PHY_SetRFReg()
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Dodm_RegConfig8723A.c24 u32 RegAddr in odm_ConfigRFReg_8723A() argument
40 ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); in odm_ConfigRFReg_8723A()
/drivers/staging/rtl8723au/include/
Dodm_interface.h58 u8 ODM_Read1Byte(struct dm_odm_t *pDM_Odm, u32 RegAddr);
59 u16 ODM_Read2Byte(struct dm_odm_t *pDM_Odm, u32 RegAddr);
60 u32 ODM_Read4Byte(struct dm_odm_t *pDM_Odm, u32 RegAddr);
61 void ODM_Write1Byte(struct dm_odm_t *pDM_Odm, u32 RegAddr, u8 Data);
62 void ODM_Write2Byte(struct dm_odm_t *pDM_Odm, u32 RegAddr, u16 Data);
63 void ODM_Write4Byte(struct dm_odm_t *pDM_Odm, u32 RegAddr, u32 Data);
64 void ODM_SetMACReg(struct dm_odm_t *pDM_Odm, u32 RegAddr, u32 BitMask, u32 Data);
65 u32 ODM_GetMACReg(struct dm_odm_t *pDM_Odm, u32 RegAddr, u32 BitMask);
66 void ODM_SetBBReg(struct dm_odm_t *pDM_Odm, u32 RegAddr, u32 BitMask, u32 Data);
67 u32 ODM_GetBBReg(struct dm_odm_t *pDM_Odm, u32 RegAddr, u32 BitMask);
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DHal8723APhyCfg.h177 u32 PHY_QueryBBReg(struct rtw_adapter *Adapter, u32 RegAddr,
179 void PHY_SetBBReg(struct rtw_adapter *Adapter, u32 RegAddr,
182 enum RF_RADIO_PATH eRFPath, u32 RegAddr,
185 enum RF_RADIO_PATH eRFPath, u32 RegAddr,
Dodm_RegConfig8723A.h19 enum RF_RADIO_PATH RF_PATH, u32 RegAddr);
/drivers/staging/rtl8188eu/include/
Dhal_intf.h217 enum rf_radio_path eRFPath, u32 RegAddr,
220 enum rf_radio_path eRFPath, u32 RegAddr,
302 u32 RegAddr, u32 BitMask);
304 enum rf_radio_path eRFPath, u32 RegAddr,
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_phy.h84 u32 RegAddr, u32 BitMask, u32 Data);
87 u32 RegAddr, u32 BitMask);
Dr8192E_phy.c222 u32 RegAddr, u32 BitMask, u32 Data) in rtl8192_phy_SetRFReg() argument
236 RegAddr); in rtl8192_phy_SetRFReg()
241 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value); in rtl8192_phy_SetRFReg()
243 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data); in rtl8192_phy_SetRFReg()
249 RegAddr); in rtl8192_phy_SetRFReg()
254 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, in rtl8192_phy_SetRFReg()
257 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data); in rtl8192_phy_SetRFReg()
263 u32 RegAddr, u32 BitMask) in rtl8192_phy_QueryRFReg() argument
274 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr); in rtl8192_phy_QueryRFReg()
278 RegAddr); in rtl8192_phy_QueryRFReg()
/drivers/tty/
Dsynclinkmp.c5544 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5546 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5549 RegAddr += 0x40; /* DMA access */ \
5551 RegAddr += 0x20; /* MSCI access */ \
5558 return *RegAddr; in read_reg()
5563 *RegAddr = Value; in write_reg()
5569 return *((u16 *)RegAddr); in read_reg16()
5575 *((u16 *)RegAddr) = Value; in write_reg16()
5580 unsigned char *RegAddr = (unsigned char *)info->statctrl_base; in read_status_reg() local
5581 return *RegAddr; in read_status_reg()
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Dsynclink.c4545 static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue ) in usc_OutDmaReg() argument
4550 outw( RegAddr + info->mbre_bit, info->io_base ); in usc_OutDmaReg()
4574 static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr ) in usc_InDmaReg() argument
4579 outw( RegAddr + info->mbre_bit, info->io_base ); in usc_InDmaReg()
4601 static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue ) in usc_OutReg() argument
4603 outw( RegAddr + info->loopback_bits, info->io_base + CCAR ); in usc_OutReg()
4626 static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr ) in usc_InReg() argument
4628 outw( RegAddr + info->loopback_bits, info->io_base + CCAR ); in usc_InReg()
/drivers/media/tuners/
Dmxl5005s.c3596 u8 RegAddr[] = { in MXL_GetInitRegister() local
3601 *count = ARRAY_SIZE(RegAddr); in MXL_GetInitRegister()
3606 RegNum[i] = RegAddr[i]; in MXL_GetInitRegister()
3621 u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106, in MXL_GetCHRegister() local
3624 u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106, in MXL_GetCHRegister() local
3633 *count = ARRAY_SIZE(RegAddr); in MXL_GetCHRegister()
3636 RegNum[i] = RegAddr[i]; in MXL_GetCHRegister()
3649 u8 RegAddr[] = {43, 136}; in MXL_GetCHRegister_ZeroIF() local
3651 *count = ARRAY_SIZE(RegAddr); in MXL_GetCHRegister_ZeroIF()
3654 RegNum[i] = RegAddr[i]; in MXL_GetCHRegister_ZeroIF()