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Searched refs:SD_CFG1 (Results 1 – 6 of 6) sorted by relevance

/drivers/mmc/host/
Drtsx_pci_sdmmc.c516 rtsx_pci_write_register(host->pcr, SD_CFG1, in sd_enable_initial_mode()
522 rtsx_pci_write_register(host->pcr, SD_CFG1, in sd_disable_initial_mode()
585 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); in sd_change_phase()
840 err = rtsx_pci_write_register(host->pcr, SD_CFG1, in sd_set_bus_width()
926 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, in sd_set_timing()
938 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, in sd_set_timing()
955 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, in sd_set_timing()
970 SD_CFG1, 0x0C, SD_20_MODE); in sd_set_timing()
Drtsx_usb_sdmmc.c546 rtsx_usb_write_register(host->ucr, SD_CFG1, in sd_enable_initial_mode()
552 rtsx_usb_write_register(host->ucr, SD_CFG1, in sd_disable_initial_mode()
613 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_RST, 0); in sd_change_phase()
919 err = rtsx_usb_write_register(host->ucr, SD_CFG1, in sd_set_bus_width()
1082 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_CFG1, in sd_set_timing()
1092 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_CFG1, in sd_set_timing()
1106 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_CFG1, in sd_set_timing()
1118 SD_CFG1, 0x0C, SD_20_MODE); in sd_set_timing()
/drivers/staging/rts5208/
Drtsx_card.h769 #define SD_CFG1 0xFDA0 macro
Dsd.c861 RTSX_WRITE_REG(chip, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); in sd_change_phase()
/drivers/mfd/
Drtsx_usb.c401 ret = rtsx_usb_write_register(ucr, SD_CFG1, in rtsx_usb_switch_clock()
Drtsx_pcr.c635 err = rtsx_pci_write_register(pcr, SD_CFG1, in rtsx_pci_switch_clock()