Searched refs:SMU_SCLK_DPM_STATE_0_CNTL_0 (Results 1 – 3 of 3) sorted by relevance
594 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix); in trinity_set_divider_value()597 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value); in trinity_set_divider_value()641 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix); in trinity_set_vid()644 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value); in trinity_set_vid()646 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix); in trinity_set_vid()649 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value); in trinity_set_vid()737 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix); in trinity_power_level_enable_disable()741 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value); in trinity_power_level_enable_disable()
28 #define TRINITY_SIZEOF_DPM_STATE_TABLE (SMU_SCLK_DPM_STATE_1_CNTL_0 - SMU_SCLK_DPM_STATE_0_CNTL_0)
34 #define SMU_SCLK_DPM_STATE_0_CNTL_0 0x1f000 macro