Home
last modified time | relevance | path

Searched refs:ch_regs (Results 1 – 10 of 10) sorted by relevance

/drivers/dma/
Dtegra20-apb-dma.c154 struct tegra_dma_channel_regs ch_regs; member
429 struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs; in tegra_dma_start() local
431 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, ch_regs->csr); in tegra_dma_start()
432 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_regs->apb_seq); in tegra_dma_start()
433 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_regs->apb_ptr); in tegra_dma_start()
434 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_regs->ahb_seq); in tegra_dma_start()
435 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_regs->ahb_ptr); in tegra_dma_start()
437 tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT, ch_regs->wcount); in tegra_dma_start()
441 ch_regs->csr | TEGRA_APBDMA_CSR_ENB); in tegra_dma_start()
475 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req->ch_regs.apb_ptr); in tegra_dma_configure_for_next()
[all …]
Dat_hdmac_regs.h69 #define ch_regs(x) (AT_DMA_CH_REGS_BASE + (x) * 0x28) /* Channel x base addr */ macro
245 void __iomem *ch_regs; member
266 __raw_readl((atchan)->ch_regs + ATC_##name##_OFFSET)
269 __raw_writel((val), (atchan)->ch_regs + ATC_##name##_OFFSET)
Dpch_dma.c132 struct pch_dma_desc_regs ch_regs[MAX_CHAN_NR]; member
773 pd->ch_regs[i].dev_addr = channel_readl(pd_chan, DEV_ADDR); in pch_dma_save_regs()
774 pd->ch_regs[i].mem_addr = channel_readl(pd_chan, MEM_ADDR); in pch_dma_save_regs()
775 pd->ch_regs[i].size = channel_readl(pd_chan, SIZE); in pch_dma_save_regs()
776 pd->ch_regs[i].next = channel_readl(pd_chan, NEXT); in pch_dma_save_regs()
796 channel_writel(pd_chan, DEV_ADDR, pd->ch_regs[i].dev_addr); in pch_dma_restore_regs()
797 channel_writel(pd_chan, MEM_ADDR, pd->ch_regs[i].mem_addr); in pch_dma_restore_regs()
798 channel_writel(pd_chan, SIZE, pd->ch_regs[i].size); in pch_dma_restore_regs()
799 channel_writel(pd_chan, NEXT, pd->ch_regs[i].next); in pch_dma_restore_regs()
Dintel_mid_dma.c260 iowrite32(first->sar, midc->ch_regs + SAR); in midc_dostart()
261 iowrite32(first->dar, midc->ch_regs + DAR); in midc_dostart()
262 iowrite32(first->lli_phys, midc->ch_regs + LLP); in midc_dostart()
263 iowrite32(first->cfg_hi, midc->ch_regs + CFG_HIGH); in midc_dostart()
264 iowrite32(first->cfg_lo, midc->ch_regs + CFG_LOW); in midc_dostart()
265 iowrite32(first->ctl_lo, midc->ch_regs + CTL_LOW); in midc_dostart()
266 iowrite32(first->ctl_hi, midc->ch_regs + CTL_HIGH); in midc_dostart()
540 cfg_lo.cfg_lo = ioread32(midc->ch_regs + CFG_LOW); in intel_mid_dma_device_control()
542 iowrite32(cfg_lo.cfg_lo, midc->ch_regs + CFG_LOW); in intel_mid_dma_device_control()
1110 midch->ch_regs = dma->dma_base + DMA_CH_SIZE * midch->ch_id; in mid_setup_dma()
Dintel_mid_dma_regs.h181 void __iomem *ch_regs; member
Dtxx9dmac.h167 void __iomem *ch_regs; member
Dtxx9dmac.c29 return dc->ch_regs; in __dma_regs()
35 return dc->ch_regs; in __dma_regs32()
1145 dc->ch_regs = &__txx9dmac_regs(dc->ddev)->CHAN[ch]; in txx9dmac_chan_probe()
1147 dc->ch_regs = &__txx9dmac_regs32(dc->ddev)->CHAN[ch]; in txx9dmac_chan_probe()
Dat_hdmac.c1479 atchan->ch_regs = atdma->regs + ch_regs(i); in at_dma_probe()
/drivers/dma/dw/
Dregs.h223 void __iomem *ch_regs; member
262 return dwc->ch_regs; in __dwc_regs()
Dcore.c1596 dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; in dw_dma_probe()