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Searched refs:channel_readl (Results 1 – 6 of 6) sorted by relevance

/drivers/dma/
Dat_hdmac_regs.h265 #define channel_readl(atchan, name) \ macro
364 channel_readl(atchan, SADDR), in vdbg_dump_regs()
365 channel_readl(atchan, DADDR), in vdbg_dump_regs()
366 channel_readl(atchan, CTRLA), in vdbg_dump_regs()
367 channel_readl(atchan, CTRLB), in vdbg_dump_regs()
368 channel_readl(atchan, CFG), in vdbg_dump_regs()
369 channel_readl(atchan, DSCR)); in vdbg_dump_regs()
Dat_hdmac.c213 channel_readl(atchan, SADDR), in atc_dostart()
214 channel_readl(atchan, DADDR), in atc_dostart()
215 channel_readl(atchan, CTRLA), in atc_dostart()
216 channel_readl(atchan, CTRLB), in atc_dostart()
217 channel_readl(atchan, DSCR)); in atc_dostart()
292 channel_readl(atchan, DSCR)); in atc_get_bytes_left()
312 count = (channel_readl(atchan, CTRLA) & ATC_BTSIZE_MAX) in atc_get_bytes_left()
483 channel_readl(atchan, DSCR)); in atc_handle_cyclic()
1630 atchan->save_dscr = channel_readl(atchan, DSCR); in atc_suspend_cyclic()
1648 atchan->save_cfg = channel_readl(atchan, CFG); in at_dma_suspend_noirq()
Dtxx9dmac.c54 #define channel_readl(dc, name) \ macro
343 if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) { in txx9dmac_dostart()
618 csr = channel_readl(dc, CSR); in txx9dmac_chan_tasklet()
636 channel_readl(dc, CSR)); in txx9dmac_chan_interrupt()
663 csr = channel_readl(dc, CSR); in txx9dmac_tasklet()
966 if (!(channel_readl(dc, CSR) & TXX9_DMA_CSR_CHNEN) && in txx9dmac_chain_dynamic()
1007 if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) { in txx9dmac_alloc_chan_resources()
1069 BUG_ON(channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT); in txx9dmac_free_chan_resources()
Dpch_dma.c122 #define channel_readl(pdc, name) \ macro
773 pd->ch_regs[i].dev_addr = channel_readl(pd_chan, DEV_ADDR); in pch_dma_save_regs()
774 pd->ch_regs[i].mem_addr = channel_readl(pd_chan, MEM_ADDR); in pch_dma_save_regs()
775 pd->ch_regs[i].size = channel_readl(pd_chan, SIZE); in pch_dma_save_regs()
776 pd->ch_regs[i].next = channel_readl(pd_chan, NEXT); in pch_dma_save_regs()
/drivers/dma/dw/
Dcore.c165 channel_readl(dwc, SAR), in dwc_dump_chan_regs()
166 channel_readl(dwc, DAR), in dwc_dump_chan_regs()
167 channel_readl(dwc, LLP), in dwc_dump_chan_regs()
168 channel_readl(dwc, CTL_HI), in dwc_dump_chan_regs()
169 channel_readl(dwc, CTL_LO)); in dwc_dump_chan_regs()
330 u32 ctlhi = channel_readl(dwc, CTL_HI); in dwc_get_sent()
331 u32 ctllo = channel_readl(dwc, CTL_LO); in dwc_get_sent()
345 llp = channel_readl(dwc, LLP); in dwc_scan_descriptors()
506 return channel_readl(dwc, SAR); in dw_dma_get_src_addr()
513 return channel_readl(dwc, DAR); in dw_dma_get_dst_addr()
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Dregs.h265 #define channel_readl(dwc, name) \ macro