Searched refs:clock_reg (Results 1 – 4 of 4) sorted by relevance
83 void __iomem *clock_reg = mch_regs_base + CRVML_REG_CLOCK; in crvml_sys_restore() local85 iowrite32(saved_clock, clock_reg); in crvml_sys_restore()86 ioread32(clock_reg); in crvml_sys_restore()93 void __iomem *clock_reg = mch_regs_base + CRVML_REG_CLOCK; in crvml_sys_save() local95 saved_clock = ioread32(clock_reg); in crvml_sys_save()127 void __iomem *clock_reg = mch_regs_base + CRVML_REG_CLOCK; in crvml_set_clock() local136 clock_val = ioread32(clock_reg) & ~CRVML_CLOCK_MASK; in crvml_set_clock()138 iowrite32(clock_val, clock_reg); in crvml_set_clock()139 ioread32(clock_reg); in crvml_set_clock()
127 unsigned long clock_reg = hwif->extra_base + 0x01; in pdc_old_enable_66MHz_clock() local128 u8 clock = inb(clock_reg); in pdc_old_enable_66MHz_clock()130 outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg); in pdc_old_enable_66MHz_clock()135 unsigned long clock_reg = hwif->extra_base + 0x01; in pdc_old_disable_66MHz_clock() local136 u8 clock = inb(clock_reg); in pdc_old_disable_66MHz_clock()138 outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg); in pdc_old_disable_66MHz_clock()
269 u32 clock_reg; member423 msg.data32 = port->clock_reg; in hss_config()1292 &port->clock_reg); in hss_hdlc_ioctl()1295 port->clock_reg = CLK42X_SPEED_2048KHZ; in hss_hdlc_ioctl()1357 port->clock_reg = CLK42X_SPEED_2048KHZ; in hss_init_one()
975 u32 clock_reg[] = { in request_even_slower_clocks() local988 for (i = 0; i < ARRAY_SIZE(clock_reg); i++) { in request_even_slower_clocks()992 val = readl(prcmu_base + clock_reg[i]); in request_even_slower_clocks()1008 writel(val, prcmu_base + clock_reg[i]); in request_even_slower_clocks()