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Searched refs:crtc2 (Results 1 – 7 of 7) sorted by relevance

/drivers/video/fbdev/matrox/
Dmatroxfb_crtc2.c150 minfo->hw.crtc2.ctl = tmp; in matroxfb_dh_restore()
164 minfo->hw.crtc2.ctl = 0x00000004; in matroxfb_dh_disable()
365 minfo->crtc2.pixclock = mt.pixclock; in matroxfb_dh_set_par()
366 minfo->crtc2.mnp = mt.mnp; in matroxfb_dh_set_par()
417 vblank->count = minfo->crtc2.vsync.cnt; in matroxfb_dh_get_vblank()
638 down_write(&minfo->crtc2.lock); in matroxfb_dh_regit()
639 oldcrtc2 = minfo->crtc2.info; in matroxfb_dh_regit()
640 minfo->crtc2.info = m2info; in matroxfb_dh_regit()
641 up_write(&minfo->crtc2.lock); in matroxfb_dh_regit()
669 struct matroxfb_dh_fb_info* crtc2; in matroxfb_dh_deregisterfb() local
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Dmatroxfb_base.c157 struct matroxfb_dh_fb_info *info = minfo->crtc2.info; in update_crtc2()
218 minfo->crtc2.vsync.cnt++; in matrox_irq()
219 wake_up_interruptible(&minfo->crtc2.vsync.wait); in matrox_irq()
282 vs = &minfo->crtc2.vsync; in matroxfb_wait_for_sync()
952 struct matroxfb_dh_fb_info* crtc2; in matroxfb_ioctl() local
954 down_read(&minfo->crtc2.lock); in matroxfb_ioctl()
955 crtc2 = minfo->crtc2.info; in matroxfb_ioctl()
956 if (crtc2) in matroxfb_ioctl()
957 crtc2->fbcon.fbops->fb_set_par(&crtc2->fbcon); in matroxfb_ioctl()
958 up_read(&minfo->crtc2.lock); in matroxfb_ioctl()
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Dmatroxfb_base.h301 struct matrox_crtc2 crtc2; member
389 } crtc2; member
471 int crtc2; member
Dmatroxfb_DAC1064.c172 c2_ctl = hw->crtc2.ctl & ~0x4007; /* Clear PLL + enable for CRTC2 */ in g450_set_plls()
176 videomnp = minfo->crtc2.mnp; in g450_set_plls()
180 } else if (minfo->crtc2.pixclock == minfo->features.pll.ref_freq) { in g450_set_plls()
206 if (c2_ctl != hw->crtc2.ctl) { in g450_set_plls()
207 hw->crtc2.ctl = c2_ctl; in g450_set_plls()
213 pxc = minfo->crtc2.pixclock; in g450_set_plls()
/drivers/gpu/drm/radeon/
Devergreen.c4372 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; in evergreen_irq_set() local
4461 crtc2 |= VBLANK_INT_MASK; in evergreen_irq_set()
4547 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); in evergreen_irq_set()
Dsi.c6025 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; in si_irq_set() local
6091 crtc2 |= VBLANK_INT_MASK; in si_irq_set()
6154 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); in si_irq_set()
Dcik.c7342 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; in cik_irq_set() local
7492 crtc2 |= VBLANK_INTERRUPT_MASK; in cik_irq_set()
7556 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); in cik_irq_set()