Searched refs:div_reg (Results 1 – 5 of 5) sorted by relevance
| /drivers/clk/socfpga/ |
| D | clk-periph.c | 37 if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()
38 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()
63 u32 div_reg[3]; in __socfpga_periph_init() local
73 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_periph_init()
75 periph_clk->div_reg = clk_mgr_base_addr + div_reg[0]; in __socfpga_periph_init()
76 periph_clk->shift = div_reg[1]; in __socfpga_periph_init()
77 periph_clk->width = div_reg[2]; in __socfpga_periph_init()
79 periph_clk->div_reg = 0; in __socfpga_periph_init()
|
| D | clk-gate.c | 111 else if (socfpgaclk->div_reg) { in socfpga_clk_recalc_rate()
112 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_clk_recalc_rate()
115 if ((int) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET) in socfpga_clk_recalc_rate()
188 u32 div_reg[3]; in __socfpga_gate_init() local
221 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_gate_init()
223 socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0]; in __socfpga_gate_init()
224 socfpga_clk->shift = div_reg[1]; in __socfpga_gate_init()
225 socfpga_clk->width = div_reg[2]; in __socfpga_gate_init()
227 socfpga_clk->div_reg = 0; in __socfpga_gate_init()
|
| D | clk.h | 46 void __iomem *div_reg; member
56 void __iomem *div_reg; member
|
| /drivers/clk/ |
| D | clk-vt8500.c | 31 void __iomem *div_reg; member
127 u32 div = readl(cdev->div_reg) & cdev->div_mask; in vt8500_dclk_recalc_rate()
198 writel(divisor, cdev->div_reg); in vt8500_dclk_set_rate()
234 u32 en_reg, div_reg; in vtwm_device_clk_init() local
264 rc = of_property_read_u32(node, "divisor-reg", &div_reg); in vtwm_device_clk_init()
266 dev_clk->div_reg = pmc_base + div_reg; in vtwm_device_clk_init()
|
| /drivers/clk/hisilicon/ |
| D | clk-hi3620.c | 242 u32 div_reg; member
258 void __iomem *div_reg; member
391 val = readl_relaxed(mclk->div_reg); in mmc_clk_set_timing()
393 writel_relaxed(val, mclk->div_reg); in mmc_clk_set_timing()
453 mclk->div_reg = base + mmc_clk->div_reg; in hisi_register_clk_mmc()
|