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Searched refs:dma_writel (Results 1 – 6 of 6) sorted by relevance

/drivers/dma/
Dpch_dma.c146 #define dma_writel(pd, name, val) \ macro
207 dma_writel(pd, CTL2, val); in pdc_enable_irq()
237 dma_writel(pd, CTL0, val); in pdc_set_dir()
254 dma_writel(pd, CTL3, val); in pdc_set_dir()
277 dma_writel(pd, CTL0, val); in pdc_set_mode()
288 dma_writel(pd, CTL3, val); in pdc_set_mode()
751 dma_writel(pd, STS0, sts0); in pd_irq()
753 dma_writel(pd, STS2, sts2); in pd_irq()
788 dma_writel(pd, CTL0, pd->regs.dma_ctl0); in pch_dma_restore_regs()
789 dma_writel(pd, CTL1, pd->regs.dma_ctl1); in pch_dma_restore_regs()
[all …]
Dat_hdmac_regs.h335 #define dma_writel(atdma, name, val) \ macro
392 dma_writel(atdma, EBCIER, ebci); in atc_setup_irq()
394 dma_writel(atdma, EBCIDR, ebci); in atc_setup_irq()
Dat_hdmac.c230 dma_writel(atdma, CHER, atchan->mask); in atc_dostart()
532 dma_writel(atdma, CHDR, in at_dma_interrupt()
1008 dma_writel(atdma, CHER, AT_DMA_SUSP(chan_id)); in atc_control()
1018 dma_writel(atdma, CHDR, AT_DMA_RES(chan_id)); in atc_control()
1033 dma_writel(atdma, CHDR, AT_DMA_RES(chan_id) | atchan->mask); in atc_control()
1375 dma_writel(atdma, EN, 0); in at_dma_off()
1378 dma_writel(atdma, EBCIDR, -1L); in at_dma_off()
1511 dma_writel(atdma, EN, AT_DMA_ENABLE); in at_dma_probe()
1669 dma_writel(atdma, CHER, atchan->mask); in atc_resume_cyclic()
1685 dma_writel(atdma, EN, AT_DMA_ENABLE); in at_dma_resume_noirq()
[all …]
Dtxx9dmac.c128 #define dma_writel(ddev, name, val) \ macro
1090 dma_writel(ddev, MCR, 0); in txx9dmac_off()
1225 dma_writel(ddev, MCR, mcr); in txx9dmac_probe()
1267 dma_writel(ddev, MCR, mcr); in txx9dmac_resume_noirq()
/drivers/dma/dw/
Dcore.c350 dma_writel(dw, CLEAR.XFER, dwc->mask); in dwc_scan_descriptors()
478 dma_writel(dw, CLEAR.ERROR, dwc->mask); in dwc_handle_error()
529 dma_writel(dw, CLEAR.BLOCK, dwc->mask); in dwc_handle_cyclic()
561 dma_writel(dw, CLEAR.BLOCK, dwc->mask); in dwc_handle_cyclic()
562 dma_writel(dw, CLEAR.ERROR, dwc->mask); in dwc_handle_cyclic()
563 dma_writel(dw, CLEAR.XFER, dwc->mask); in dwc_handle_cyclic()
1100 dma_writel(dw, CFG, 0); in dw_dma_off()
1117 dma_writel(dw, CFG, DW_CFG_DMA_EN); in dw_dma_on()
1474 dma_writel(dw, CLEAR.BLOCK, dwc->mask); in dw_dma_cyclic_free()
1475 dma_writel(dw, CLEAR.ERROR, dwc->mask); in dw_dma_cyclic_free()
[all …]
Dregs.h298 #define dma_writel(dw, name, val) \ macro
302 dma_writel(dw, reg, ((mask) << 8) | (mask))
304 dma_writel(dw, reg, ((mask) << 8) | 0)