Searched refs:fp0 (Results 1 – 14 of 14) sorted by relevance
/drivers/gpu/drm/gma500/ |
D | mdfld_device.c | 198 pipe->fp0 = PSB_RVDC32(map->fp0); in mdfld_save_display_registers() 286 PSB_WVDC32(pipe->fp0, map->fp0); in mdfld_restore_display_registers() 302 PSB_WVDC32(pipe->fp0, map->fp0); in mdfld_restore_display_registers() 449 .fp0 = MRST_FPA0, 472 .fp0 = MDFLD_DPLL_DIV0, 494 .fp0 = MRST_FPA0, /* This is what the old code did ?? */
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D | psb_intel_display.c | 223 REG_WRITE(map->fp0, fp); in psb_intel_crtc_mode_set() 258 REG_WRITE(map->fp0, fp); in psb_intel_crtc_mode_set() 323 fp = REG_READ(map->fp0); in psb_intel_crtc_clock_get() 332 fp = p->fp0; in psb_intel_crtc_clock_get()
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D | oaktrail_device.c | 210 p->fp0 = PSB_RVDC32(MRST_FPA0); in oaktrail_save_display_registers() 325 PSB_WVDC32(p->fp0, MRST_FPA0); in oaktrail_restore_display_registers() 465 .fp0 = MRST_FPA0, 489 .fp0 = FPB0,
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D | psb_device.c | 264 .fp0 = FPA0, 288 .fp0 = FPB0,
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D | gma_display.c | 573 crtc_state->saveFP0 = REG_READ(map->fp0); in gma_crtc_save() 620 REG_WRITE(map->fp0, crtc_state->saveFP0); in gma_crtc_restore() 621 REG_READ(map->fp0); in gma_crtc_restore()
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D | cdv_device.c | 526 .fp0 = FPA0, 551 .fp0 = FPB0,
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D | oaktrail_crtc.c | 562 REG_WRITE_WITH_AUX(map->fp0, fp, i); in oaktrail_crtc_mode_set() 571 REG_WRITE_WITH_AUX(map->fp0, fp, i); in oaktrail_crtc_mode_set()
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D | psb_drv.h | 277 u32 fp0; member 311 u32 fp0; member
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D | mdfld_intel_display.c | 940 REG_WRITE(map->fp0, 0); in mdfld_crtc_mode_set() 992 REG_WRITE(map->fp0, fp); in mdfld_crtc_mode_set()
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D | cdv_intel_display.c | 865 fp = REG_READ(map->fp0); in cdv_intel_crtc_clock_get() 873 fp = p->fp0; in cdv_intel_crtc_clock_get()
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/drivers/video/fbdev/intelfb/ |
D | intelfbhw.c | 1048 u32 *dpll, *fp0, *fp1; in intelfbhw_mode_to_hw() local 1064 fp0 = &hw->fpb0; in intelfbhw_mode_to_hw() 1076 fp0 = &hw->fpa0; in intelfbhw_mode_to_hw() 1146 *fp0 = (n << FP_N_DIVISOR_SHIFT) | in intelfbhw_mode_to_hw() 1149 *fp1 = *fp0; in intelfbhw_mode_to_hw() 1284 const u32 *dpll, *fp0, *fp1, *pipe_conf; in intelfbhw_program_mode() local 1307 fp0 = &hw->fpb0; in intelfbhw_program_mode() 1331 fp0 = &hw->fpa0; in intelfbhw_program_mode() 1406 OUTREG(fp0_reg, *fp0); in intelfbhw_program_mode()
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/drivers/gpu/drm/i915/ |
D | intel_display.c | 4855 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0); in i9xx_set_pll_dividers() 5601 crtc->config.dpll_hw_state.fp0 = fp; in i9xx_update_pll_dividers() 6506 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); in i9xx_get_pipe_config() 7262 intel_crtc->config.dpll_hw_state.fp0 = fp; in ironlake_crtc_mode_set() 8868 fp = pipe_config->dpll_hw_state.fp0; in i9xx_crtc_clock_get() 9011 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); in intel_crtc_mode_get() 10826 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); in intel_pipe_config_compare() 11703 hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); in ibx_pch_dpll_get_hw_state() 11712 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); in ibx_pch_dpll_mode_set()
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D | i915_drv.h | 214 uint32_t fp0; member
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D | i915_debugfs.c | 2637 seq_printf(m, " fp0: 0x%08x\n", pll->hw_state.fp0); in i915_shared_dplls_info()
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