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Searched refs:intel_crtc (Results 1 – 22 of 22) sorted by relevance

/drivers/gpu/drm/i915/
Dintel_display.c80 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
82 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
91 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
92 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
93 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
99 static void vlv_prepare_pll(struct intel_crtc *crtc);
100 static void chv_prepare_pll(struct intel_crtc *crtc);
868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_active() local
879 return intel_crtc->active && crtc->primary->fb && in intel_crtc_active()
880 intel_crtc->config.adjusted_mode.crtc_clock; in intel_crtc_active()
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Dintel_sprite.c49 static bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count) in intel_pipe_update_start()
115 static void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count) in intel_pipe_update_end()
130 static void intel_update_primary_plane(struct intel_crtc *crtc) in intel_update_primary_plane()
152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in vlv_update_plane() local
248 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); in vlv_update_plane()
250 intel_update_primary_plane(intel_crtc); in vlv_update_plane()
265 intel_flush_primary_plane(dev_priv, intel_crtc->plane); in vlv_update_plane()
268 intel_pipe_update_end(intel_crtc, start_vbl_count); in vlv_update_plane()
277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in vlv_disable_plane() local
283 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); in vlv_disable_plane()
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Dintel_dsi_cmd.c56 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); in print_stat() local
57 enum pipe pipe = intel_crtc->pipe; in print_stat()
112 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); in dsi_hs_mode_enable() local
113 enum pipe pipe = intel_crtc->pipe; in dsi_hs_mode_enable()
133 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); in dsi_vc_send_short() local
134 enum pipe pipe = intel_crtc->pipe; in dsi_vc_send_short()
175 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); in dsi_vc_send_long() local
176 enum pipe pipe = intel_crtc->pipe; in dsi_vc_send_long()
294 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); in dsi_read_data_return() local
295 enum pipe pipe = intel_crtc->pipe; in dsi_read_data_return()
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Dintel_ddi.c278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in hsw_fdi_link_train() local
295 FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); in hsw_fdi_link_train()
305 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config.ddi_pll_sel); in hsw_fdi_link_train()
306 WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL); in hsw_fdi_link_train()
324 ((intel_crtc->config.fdi_lanes - 1) << 1) | in hsw_fdi_link_train()
409 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_ddi_get_crtc_encoder() local
420 pipe_name(intel_crtc->pipe)); in intel_ddi_get_crtc_encoder()
744 hsw_ddi_pll_select(struct intel_crtc *intel_crtc, in hsw_ddi_pll_select() argument
759 intel_crtc->config.dpll_hw_state.wrpll = val; in hsw_ddi_pll_select()
761 pll = intel_get_shared_dpll(intel_crtc); in hsw_ddi_pll_select()
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Dintel_fbdev.c268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_fb_gamma_set() local
270 intel_crtc->lut_r[regno] = red >> 8; in intel_crtc_fb_gamma_set()
271 intel_crtc->lut_g[regno] = green >> 8; in intel_crtc_fb_gamma_set()
272 intel_crtc->lut_b[regno] = blue >> 8; in intel_crtc_fb_gamma_set()
278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_fb_gamma_get() local
280 *red = intel_crtc->lut_r[regno] << 8; in intel_crtc_fb_gamma_get()
281 *green = intel_crtc->lut_g[regno] << 8; in intel_crtc_fb_gamma_get()
282 *blue = intel_crtc->lut_b[regno] << 8; in intel_crtc_fb_gamma_get()
515 struct intel_crtc *intel_crtc; in intel_fbdev_init_bios() local
524 intel_crtc = to_intel_crtc(crtc); in intel_fbdev_init_bios()
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Dintel_hdmi.c176 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); in ibx_write_infoframe() local
177 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); in ibx_write_infoframe()
191 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); in ibx_write_infoframe()
196 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); in ibx_write_infoframe()
214 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); in cpt_write_infoframe() local
215 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); in cpt_write_infoframe()
232 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); in cpt_write_infoframe()
237 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); in cpt_write_infoframe()
255 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); in vlv_write_infoframe() local
256 int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); in vlv_write_infoframe()
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Dintel_dsi.c108 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); in intel_dsi_device_ready() local
109 int pipe = intel_crtc->pipe; in intel_dsi_device_ready()
141 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); in intel_dsi_enable() local
143 int pipe = intel_crtc->pipe; in intel_dsi_enable()
173 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); in intel_dsi_pre_enable() local
174 enum pipe pipe = intel_crtc->pipe; in intel_dsi_pre_enable()
186 intel_crtc->config.dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV | in intel_dsi_pre_enable()
238 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); in intel_dsi_disable() local
240 int pipe = intel_crtc->pipe; in intel_dsi_disable()
284 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); in intel_dsi_clear_device_ready() local
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Dintel_drv.h136 struct intel_crtc *new_crtc;
393 struct intel_crtc { struct
509 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
761 int intel_get_crtc_scanline(struct intel_crtc *crtc);
780 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
781 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
782 bool intel_ddi_pll_select(struct intel_crtc *crtc);
871 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
877 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc);
878 void intel_put_shared_dpll(struct intel_crtc *crtc);
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Dintel_pm.c97 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in i8xx_enable_fbc() local
121 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane); in i8xx_enable_fbc()
137 cfb_pitch, crtc->y, plane_name(intel_crtc->plane)); in i8xx_enable_fbc()
153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in g4x_enable_fbc() local
156 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN; in g4x_enable_fbc()
168 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); in g4x_enable_fbc()
224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_enable_fbc() local
227 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane); in ironlake_enable_fbc()
259 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); in ironlake_enable_fbc()
290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in gen7_enable_fbc() local
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Dintel_dp.c1022 struct intel_crtc *intel_crtc = encoder->new_crtc; in intel_dp_compute_config() local
1045 intel_gmch_panel_fitting(intel_crtc, pipe_config, in intel_dp_compute_config()
1048 intel_pch_panel_fitting(intel_crtc, pipe_config, in intel_dp_compute_config()
1152 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); in ironlake_set_pll_cpu_edp()
1185 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); in intel_dp_prepare()
1877 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); in intel_dp_get_config()
1974 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); in intel_edp_psr_write_vsc()
2085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_edp_psr_match_conditions() local
2107 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) & in intel_edp_psr_match_conditions()
2113 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { in intel_edp_psr_match_conditions()
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Dintel_dp_mst.c140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_mst_pre_enable_dp() local
160 I915_WRITE(PORT_CLK_SEL(port), intel_crtc->config.ddi_pll_sel); in intel_mst_pre_enable_dp()
173 intel_mst->port, intel_crtc->config.pbn, &slots); in intel_mst_pre_enable_dp()
223 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); in intel_dp_mst_enc_get_config()
Dintel_lvds.c140 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); in intel_pre_enable_lvds()
288 struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc; in intel_lvds_compute_config() local
292 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { in intel_lvds_compute_config()
320 intel_pch_panel_fitting(intel_crtc, pipe_config, in intel_lvds_compute_config()
323 intel_gmch_panel_fitting(intel_crtc, pipe_config, in intel_lvds_compute_config()
Di915_irq.c236 struct intel_crtc *crtc; in ivb_can_enable_err_int()
295 struct intel_crtc *crtc; in cpt_can_enable_serr_int()
312 struct intel_crtc *crtc; in i9xx_check_fifo_underruns()
492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in __intel_set_cpu_fifo_underrun_reporting() local
497 old = !intel_crtc->cpu_fifo_underrun_disabled; in __intel_set_cpu_fifo_underrun_reporting()
498 intel_crtc->cpu_fifo_underrun_disabled = !enable; in __intel_set_cpu_fifo_underrun_reporting()
531 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in __cpu_fifo_underrun_reporting_enabled() local
533 return !intel_crtc->cpu_fifo_underrun_disabled; in __cpu_fifo_underrun_reporting_enabled()
556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_set_pch_fifo_underrun_reporting() local
571 old = !intel_crtc->pch_fifo_underrun_disabled; in intel_set_pch_fifo_underrun_reporting()
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Dintel_tv.c1024 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); in intel_tv_pre_enable() local
1068 if (intel_crtc->pipe == 1) in intel_tv_pre_enable()
1119 assert_pipe_disabled(dev_priv, intel_crtc->pipe); in intel_tv_pre_enable()
1182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_tv_detect_type() local
1205 if (intel_crtc->pipe == 1) in intel_tv_detect_type()
Di915_trace.h21 TP_PROTO(struct intel_crtc *crtc, u32 min, u32 max),
47 TP_PROTO(struct intel_crtc *crtc, u32 min, u32 max, u32 frame),
72 TP_PROTO(struct intel_crtc *crtc, u32 frame),
Dintel_panel.c100 intel_pch_panel_fitting(struct intel_crtc *intel_crtc, in intel_pch_panel_fitting() argument
303 void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc, in intel_gmch_panel_fitting() argument
307 struct drm_device *dev = intel_crtc->base.dev; in intel_gmch_panel_fitting()
361 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) | in intel_gmch_panel_fitting()
Dintel_dvo.c184 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); in intel_enable_dvo()
297 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); in intel_dvo_pre_enable()
Di915_debugfs.c521 struct intel_crtc *crtc; in i915_gem_pageflip_info()
2354 struct intel_crtc *intel_crtc, in intel_encoder_info() argument
2359 struct drm_crtc *crtc = &intel_crtc->base; in intel_encoder_info()
2382 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) in intel_crtc_info() argument
2386 struct drm_crtc *crtc = &intel_crtc->base; in intel_crtc_info()
2396 intel_encoder_info(m, intel_crtc, intel_encoder); in intel_crtc_info()
2507 struct intel_crtc *crtc; in i915_display_info()
2934 struct intel_crtc *crtc; in i9xx_pipe_crc_auto_source()
3176 struct intel_crtc *crtc = in hsw_trans_edp_pipe_A_crc_wa()
3202 struct intel_crtc *crtc = in hsw_undo_trans_edp_pipe_A_crc_wa()
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Dintel_sdvo.c997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_sdvo_set_avi_infoframe() local
1010 if (intel_crtc->config.limited_color_range) in intel_sdvo_set_avi_infoframe()
1182 struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc); in intel_sdvo_pre_enable()
1473 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); in intel_enable_sdvo() local
1484 temp |= SDVO_PIPE_SEL(intel_crtc->pipe); in intel_enable_sdvo()
1489 intel_wait_for_vblank(dev, intel_crtc->pipe); in intel_enable_sdvo()
Dintel_overlay.c172 struct intel_crtc *crtc;
833 struct intel_crtc *crtc) in check_overlay_possible_on_crtc()
1043 struct intel_crtc *crtc; in intel_overlay_put_image()
Di915_drv.h176 #define for_each_intel_crtc(dev, intel_crtc) \ argument
177 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
431 struct intel_crtc;
467 bool (*get_pipe_config)(struct intel_crtc *,
469 void (*get_plane_config)(struct intel_crtc *,
Dintel_crt.c159 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); in intel_crt_set_dpms()