| /drivers/gpu/drm/exynos/ |
| D | exynos_dp_core.c | 282 int lane, lane_count, pll_tries, retval; in exynos_dp_link_start() local
284 lane_count = dp->link_train.lane_count; in exynos_dp_link_start()
289 for (lane = 0; lane < lane_count; lane++) in exynos_dp_link_start()
294 exynos_dp_set_lane_count(dp, dp->link_train.lane_count); in exynos_dp_link_start()
298 buf[1] = dp->link_train.lane_count; in exynos_dp_link_start()
305 for (lane = 0; lane < lane_count; lane++) in exynos_dp_link_start()
331 for (lane = 0; lane < lane_count; lane++) in exynos_dp_link_start()
336 lane_count, buf); in exynos_dp_link_start()
349 static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count) in exynos_dp_clock_recovery_ok() argument
354 for (lane = 0; lane < lane_count; lane++) { in exynos_dp_clock_recovery_ok()
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| D | exynos_dp_core.h | 133 enum link_lane_count_type lane_count; member
141 u8 lane_count; member
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| /drivers/gpu/drm/gma500/ |
| D | cdv_intel_dp.c | 70 uint8_t lane_count; member
706 int lane_count, clock; in cdv_intel_dp_mode_fixup() local
719 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { in cdv_intel_dp_mode_fixup()
721 int link_avail = cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws[clock]), lane_count); in cdv_intel_dp_mode_fixup()
725 intel_dp->lane_count = lane_count; in cdv_intel_dp_mode_fixup()
729 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
737 intel_dp->lane_count = max_lane_count; in cdv_intel_dp_mode_fixup()
742 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
799 int lane_count = 4, bpp = 24; in cdv_intel_dp_set_m_n() local
816 lane_count = intel_dp->lane_count; in cdv_intel_dp_set_m_n()
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| D | mdfld_dsi_dpi.c | 470 int lane_count = dsi_config->lane_count; in mdfld_dsi_dpi_controller_init() local
485 val = lane_count; in mdfld_dsi_dpi_controller_init()
506 (8 * lane_count)) & DSI_HS_TX_TIMEOUT_MASK); in mdfld_dsi_dpi_controller_init()
523 dsi_config->lane_count, dsi_config->bpp); in mdfld_dsi_dpi_controller_init()
749 dsi_config->lane_count, in mdfld_mipi_set_video_timing()
773 int lane_count = dsi_config->lane_count; in mdfld_mipi_config() local
787 REG_WRITE(MIPI_DSI_FUNC_PRG_REG(pipe), 0x00000200 | lane_count); in mdfld_mipi_config()
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| D | mdfld_dsi_output.c | 434 config->lane_count = 4; in mdfld_dsi_get_default_config()
436 config->lane_count = 2; in mdfld_dsi_get_default_config()
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| D | mdfld_dsi_output.h | 260 int lane_count; member
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| /drivers/gpu/drm/i915/ |
| D | intel_dsi_pll.c | 57 int lane_count, bool eotp) in dsi_rr_formula() argument
122 bytes_per_x_frames_x_lanes = bytes_per_x_frames / lane_count; in dsi_rr_formula()
137 static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count) in dsi_clk_from_pclk() argument
158 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); in dsi_clk_from_pclk()
236 intel_dsi->lane_count); in vlv_configure_dsi_pll()
375 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp); in vlv_get_dsi_pclk()
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| D | intel_dsi.c | 426 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, in txbyteclkhs() argument
430 8 * 100), lane_count); in txbyteclkhs()
442 unsigned int lane_count = intel_dsi->lane_count; in set_dsi_timings() local
456 hactive = txbyteclkhs(hactive, bpp, lane_count, in set_dsi_timings()
458 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); in set_dsi_timings()
459 hsync = txbyteclkhs(hsync, bpp, lane_count, in set_dsi_timings()
461 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); in set_dsi_timings()
515 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; in intel_dsi_prepare()
548 intel_dsi->lane_count, in intel_dsi_prepare()
554 bpp, intel_dsi->lane_count, in intel_dsi_prepare()
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| D | intel_dp_mst.c | 40 int lane_count, slots; in intel_dp_mst_compute_config() local
53 lane_count = drm_dp_max_lane_count(intel_dp->dpcd); in intel_dp_mst_compute_config()
55 intel_dp->lane_count = lane_count; in intel_dp_mst_compute_config()
77 intel_link_compute_m_n(bpp, lane_count, in intel_dp_mst_compute_config()
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| D | intel_dsi_panel_vbt.c | 287 intel_dsi->lane_count = mipi_config->lane_cnt + 1; in generic_init()
315 (pclk * bits_per_pixel) / intel_dsi->lane_count; in generic_init()
338 bitrate = (pclk * bits_per_pixel) / intel_dsi->lane_count; in generic_init()
356 switch (intel_dsi->lane_count) { in generic_init()
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| D | intel_dp.c | 1024 int lane_count, clock; in intel_dp_compute_config() local
1086 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) { in intel_dp_compute_config()
1089 lane_count); in intel_dp_compute_config()
1117 intel_dp->lane_count = lane_count; in intel_dp_compute_config()
1122 intel_dp->link_bw, intel_dp->lane_count, in intel_dp_compute_config()
1127 intel_link_compute_m_n(bpp, lane_count, in intel_dp_compute_config()
1135 intel_link_compute_m_n(bpp, lane_count, in intel_dp_compute_config()
1212 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); in intel_dp_prepare()
3180 for (lane = 0; lane < intel_dp->lane_count; lane++) { in intel_get_adjust_train()
3391 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); in intel_dp_set_link_train()
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| D | intel_dsi.h | 91 unsigned int lane_count; member
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| D | intel_ddi.c | 401 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); in intel_ddi_init_dp_buf_reg()
923 temp |= DDI_PORT_WIDTH(intel_dp->lane_count); in intel_ddi_enable_transcoder_func()
932 temp |= DDI_PORT_WIDTH(intel_dp->lane_count); in intel_ddi_enable_transcoder_func()
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| D | intel_drv.h | 557 uint8_t lane_count; member
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| /drivers/gpu/drm/ |
| D | drm_dp_helper.c | 250 int lane_count) in drm_dp_channel_eq_ok() argument
260 for (lane = 0; lane < lane_count; lane++) { in drm_dp_channel_eq_ok()
270 int lane_count) in drm_dp_clock_recovery_ok() argument
275 for (lane = 0; lane < lane_count; lane++) { in drm_dp_clock_recovery_ok()
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| /drivers/edac/ |
| D | ppc4xx_edac.c | 444 const unsigned int lane_count = 16; in ppc4xx_edac_generate_lane_message() local
455 for (lanes = 0, lane = first_lane; lane < lane_count; lane++) { in ppc4xx_edac_generate_lane_message()
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| /drivers/gpu/drm/radeon/ |
| D | atombios_dp.c | 241 int lane_count, in dp_get_adjust_train() argument
248 for (lane = 0; lane < lane_count; lane++) { in dp_get_adjust_train()
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