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Searched refs:nvif_wr32 (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/nouveau/dispnv04/
Doverlay.c138 nvif_wr32(dev, NV_PVIDEO_BASE(flip), 0); in nv10_update_plane()
139 nvif_wr32(dev, NV_PVIDEO_OFFSET_BUFF(flip), nv_fb->nvbo->bo.offset); in nv10_update_plane()
140 nvif_wr32(dev, NV_PVIDEO_SIZE_IN(flip), src_h << 16 | src_w); in nv10_update_plane()
141 nvif_wr32(dev, NV_PVIDEO_POINT_IN(flip), src_y << 16 | src_x); in nv10_update_plane()
142 nvif_wr32(dev, NV_PVIDEO_DS_DX(flip), (src_w << 20) / crtc_w); in nv10_update_plane()
143 nvif_wr32(dev, NV_PVIDEO_DT_DY(flip), (src_h << 20) / crtc_h); in nv10_update_plane()
144 nvif_wr32(dev, NV_PVIDEO_POINT_OUT(flip), crtc_y << 16 | crtc_x); in nv10_update_plane()
145 nvif_wr32(dev, NV_PVIDEO_SIZE_OUT(flip), crtc_h << 16 | crtc_w); in nv10_update_plane()
157 nvif_wr32(dev, NV_PVIDEO_UVPLANE_BASE(flip), 0); in nv10_update_plane()
158 nvif_wr32(dev, NV_PVIDEO_UVPLANE_OFFSET_BUFF(flip), in nv10_update_plane()
[all …]
Dhw.c677 nvif_wr32(device, NV_PVIDEO_STOP, 1); in nv_load_state_ext()
678 nvif_wr32(device, NV_PVIDEO_INTR_EN, 0); in nv_load_state_ext()
679 nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(0), 0); in nv_load_state_ext()
680 nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(1), 0); in nv_load_state_ext()
681 nvif_wr32(device, NV_PVIDEO_LIMIT(0), device->info.ram_size - 1); in nv_load_state_ext()
682 nvif_wr32(device, NV_PVIDEO_LIMIT(1), device->info.ram_size - 1); in nv_load_state_ext()
683 nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), device->info.ram_size - 1); in nv_load_state_ext()
684 nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), device->info.ram_size - 1); in nv_load_state_ext()
685 nvif_wr32(device, NV_PBUS_POWERCTRL_2, 0); in nv_load_state_ext()
Ddac.c261 nvif_wr32(device, NV_PBUS_POWERCTRL_2, saved_powerctrl_2 & 0xd7ffffff); in nv17_dac_sample_load()
264 nvif_wr32(device, NV_PBUS_POWERCTRL_4, saved_powerctrl_4 & 0xffffffcf); in nv17_dac_sample_load()
319 nvif_wr32(device, NV_PBUS_POWERCTRL_4, saved_powerctrl_4); in nv17_dac_sample_load()
320 nvif_wr32(device, NV_PBUS_POWERCTRL_2, saved_powerctrl_2); in nv17_dac_sample_load()
Dtvnv17.h134 nvif_wr32(device, reg, val); in nv_write_ptv()
Dhw.h77 nvif_wr32(device, reg, val); in NVWriteCRTC()
97 nvif_wr32(device, reg, val); in NVWriteRAMDAC()
/drivers/gpu/drm/nouveau/
Dnouveau_vga.c19 nvif_wr32(device, 0x088060, state); in nouveau_vga_set_decode()
22 nvif_wr32(device, 0x088054, state); in nouveau_vga_set_decode()
24 nvif_wr32(device, 0x001854, state); in nouveau_vga_set_decode()
Dnouveau_backlight.c58 nvif_wr32(device, NV40_PMC_BACKLIGHT, in nv40_set_intensity()
120 nvif_wr32(device, NV50_PDISP_SOR_PWM_CTL(or), in nv50_set_intensity()
161 nvif_wr32(device, NV50_PDISP_SOR_PWM_CTL(or), val | in nva3_set_intensity()
Dnouveau_agp.c136 nvif_wr32(device, NV04_PBUS_PCI_NV_19, 0); in nouveau_agp_reset()
143 nvif_wr32(device, NV04_PBUS_PCI_NV_1, save[0]); in nouveau_agp_reset()
Dnouveau_dma.h143 nvif_wr32(chan, chan->user_put, ((val) << 2) + chan->push.vma.offset); \
Dnouveau_dma.c106 nvif_wr32(chan, 0x8c, chan->dma.ib_put); in nv50_dma_push()
Dnouveau_bios.c253 nvif_wr32(device, NV_PBUS_POWERCTRL_2, 0); in call_lvds_script()
1937 nvif_wr32(device, 0x00001304, ROM32(bios->data[hwsq_entry_offset])); in load_nv17_hwsq_ucode_entry()
1942 nvif_wr32(device, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4])); in load_nv17_hwsq_ucode_entry()
1945 nvif_wr32(device, NV_PBUS_DEBUG_4, nvif_rd32(device, NV_PBUS_DEBUG_4) | 0x18); in load_nv17_hwsq_ucode_entry()
Dnv50_display.c406 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000); in evo_wait()
423 nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2); in evo_kick()
1284 nvif_wr32(&chan->user, 0x0084, (y << 16) | (x & 0xffff)); in nv50_crtc_cursor_move()
1285 nvif_wr32(&chan->user, 0x0080, 0x00000000); in nv50_crtc_cursor_move()
/drivers/gpu/drm/nouveau/nvif/
Dobject.h62 #define nvif_wr32(a,b,c) nvif_wr((a), 32, (b), (u32)(c)) macro
65 nvif_wr32(nvif_object(a), (b), (_v & ~(c)) | (d)); \