| /drivers/clk/samsung/ |
| D | clk-pll.c | 77 u32 pll_con, mdiv, pdiv, sdiv; in samsung_pll2126_recalc_rate() local
82 pdiv = (pll_con >> PLL2126_PDIV_SHIFT) & PLL2126_PDIV_MASK; in samsung_pll2126_recalc_rate()
86 do_div(fvco, (pdiv + 2) << sdiv); in samsung_pll2126_recalc_rate()
110 u32 pll_con, mdiv, pdiv, sdiv; in samsung_pll3000_recalc_rate() local
115 pdiv = (pll_con >> PLL3000_PDIV_SHIFT) & PLL3000_PDIV_MASK; in samsung_pll3000_recalc_rate()
119 do_div(fvco, pdiv << sdiv); in samsung_pll3000_recalc_rate()
147 u32 mdiv, pdiv, sdiv, pll_con; in samsung_pll35xx_recalc_rate() local
152 pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK; in samsung_pll35xx_recalc_rate()
156 do_div(fvco, (pdiv << sdiv)); in samsung_pll35xx_recalc_rate()
169 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv); in samsung_pll35xx_mp_change()
[all …]
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| D | clk-pll.h | 42 .pdiv = (_p), \
50 .pdiv = (_p), \
59 .pdiv = (_p), \
68 .pdiv = (_p), \
78 .pdiv = (_p), \
90 unsigned int pdiv; member
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| D | clk-exynos3250.c | 1005 exynos3250_dmc_plls[bpll].rate_table[0].pdiv, in exynos3250_cmu_dmc_init()
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| /drivers/clk/tegra/ |
| D | clk-tegra124.c | 167 { .pdiv = 1, .hw_val = 0 },
168 { .pdiv = 2, .hw_val = 1 },
169 { .pdiv = 3, .hw_val = 2 },
170 { .pdiv = 4, .hw_val = 3 },
171 { .pdiv = 5, .hw_val = 4 },
172 { .pdiv = 6, .hw_val = 5 },
173 { .pdiv = 8, .hw_val = 6 },
174 { .pdiv = 10, .hw_val = 7 },
175 { .pdiv = 12, .hw_val = 8 },
176 { .pdiv = 16, .hw_val = 9 },
[all …]
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| D | clk-tegra114.c | 187 { .pdiv = 1, .hw_val = 0 },
188 { .pdiv = 2, .hw_val = 1 },
189 { .pdiv = 3, .hw_val = 2 },
190 { .pdiv = 4, .hw_val = 3 },
191 { .pdiv = 5, .hw_val = 4 },
192 { .pdiv = 6, .hw_val = 5 },
193 { .pdiv = 8, .hw_val = 6 },
194 { .pdiv = 10, .hw_val = 7 },
195 { .pdiv = 12, .hw_val = 8 },
196 { .pdiv = 16, .hw_val = 9 },
[all …]
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| D | clk-pll.c | 365 while (p_tohw->pdiv) { in _p_div_to_hw()
366 if (p_div <= p_tohw->pdiv) in _p_div_to_hw()
381 while (p_tohw->pdiv) { in _hw_to_p_div()
383 return p_tohw->pdiv; in _hw_to_p_div()
653 int pdiv; in clk_pll_recalc_rate() local
674 pdiv = _hw_to_p_div(hw, cfg.p); in clk_pll_recalc_rate()
675 if (pdiv < 0) { in clk_pll_recalc_rate()
677 pdiv = 1; in clk_pll_recalc_rate()
680 cfg.m *= pdiv; in clk_pll_recalc_rate()
1734 while (p_tohw->pdiv) { in tegra_clk_register_pllc()
[all …]
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| D | clk-tegra20.c | 373 { .pdiv = 1, .hw_val = 1 },
374 { .pdiv = 2, .hw_val = 0 },
375 { .pdiv = 0, .hw_val = 0 },
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| D | clk-tegra30.c | 330 { .pdiv = 1, .hw_val = 1 },
331 { .pdiv = 2, .hw_val = 0 },
332 { .pdiv = 0, .hw_val = 0 },
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| D | clk.h | 128 u8 pdiv; member
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| /drivers/cpufreq/ |
| D | s3c2412-cpufreq.c | 43 unsigned int hdiv, pdiv, armdiv, dvs; in s3c2412_cpufreq_calcdivs() local
91 pdiv = (hclk > cfg->max.pclk) ? 2 : 1; in s3c2412_cpufreq_calcdivs()
93 if ((hclk / pdiv) > cfg->max.pclk) in s3c2412_cpufreq_calcdivs()
94 pdiv++; in s3c2412_cpufreq_calcdivs()
96 cfg->freq.pclk = hclk / pdiv; in s3c2412_cpufreq_calcdivs()
98 s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv); in s3c2412_cpufreq_calcdivs()
100 if (pdiv > 2) in s3c2412_cpufreq_calcdivs()
103 pdiv *= hdiv; in s3c2412_cpufreq_calcdivs()
108 cfg->divs.p_divisor = pdiv * armdiv; in s3c2412_cpufreq_calcdivs()
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| D | s3c2440-cpufreq.c | 57 unsigned int hdiv, pdiv; in s3c2440_cpufreq_calcdivs() local
91 pdiv = (hclk > cfg->max.pclk) ? 2 : 1; in s3c2440_cpufreq_calcdivs()
93 if ((hclk / pdiv) > cfg->max.pclk) in s3c2440_cpufreq_calcdivs()
94 pdiv++; in s3c2440_cpufreq_calcdivs()
96 s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv); in s3c2440_cpufreq_calcdivs()
98 if (pdiv > 2) in s3c2440_cpufreq_calcdivs()
101 pdiv *= hdiv; in s3c2440_cpufreq_calcdivs()
122 cfg->divs.p_divisor = pdiv; in s3c2440_cpufreq_calcdivs()
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| D | s3c2410-cpufreq.c | 49 unsigned int hdiv, pdiv; in s3c2410_cpufreq_calcdivs() local
68 pdiv = (hclk > cfg->max.pclk) ? 2 : 1; in s3c2410_cpufreq_calcdivs()
69 pclk = hclk / pdiv; in s3c2410_cpufreq_calcdivs()
76 pdiv *= hdiv; in s3c2410_cpufreq_calcdivs()
79 cfg->divs.p_divisor = pdiv; in s3c2410_cpufreq_calcdivs()
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| /drivers/clk/st/ |
| D | clk-flexgen.c | 25 struct clk_divider pdiv; member
123 struct clk_hw *pdiv_hw = &flexgen->pdiv.hw; in flexgen_recalc_rate()
139 struct clk_hw *pdiv_hw = &flexgen->pdiv.hw; in flexgen_set_rate()
204 fgxbar->pdiv.lock = lock; in clk_register_flexgen()
205 fgxbar->pdiv.reg = reg + 0x58 + idx * 4; in clk_register_flexgen()
206 fgxbar->pdiv.width = 10; in clk_register_flexgen()
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| D | clkgen-pll.c | 48 struct clkgen_field pdiv; member
75 .pdiv = CLKGEN_FIELD(0x0, C65_PDIV_MASK, 16),
277 unsigned long mdiv, ndiv, pdiv; in recalc_stm_pll800c65() local
284 pdiv = CLKGEN_READ(pll, pdiv); in recalc_stm_pll800c65()
292 rate = (unsigned long)div64_u64(res, mdiv * (1 << pdiv)); in recalc_stm_pll800c65()
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| D | clkgen-fsyn.c | 529 unsigned long pdiv = 1, n; in clk_fs660c32_vco_get_params() local
543 n = output * pdiv / input; in clk_fs660c32_vco_get_params()
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| /drivers/gpu/drm/sti/ |
| D | sti_hdmi_tx3g0c55phy.c | 139 u32 mdiv, ndiv, pdiv, val; in enable_pll_rejection() local
166 pdiv = 4; in enable_pll_rejection()
170 pdiv = 2; in enable_pll_rejection()
182 val |= (pdiv << REJECTION_PLL_HDMI_PDIV_SHIFT) | in enable_pll_rejection()
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| /drivers/net/wireless/b43/ |
| D | phy_lp.c | 562 lpphy->pdiv = 1; in lpphy_2062_init()
565 lpphy->pdiv = 2; in lpphy_2062_init()
569 tmp = (((800000000 * lpphy->pdiv + crystalfreq) / in lpphy_2062_init()
573 tmp = (((100 * crystalfreq + 16000000 * lpphy->pdiv) / in lpphy_2062_init()
574 (32000000 * lpphy->pdiv)) - 1) & 0xFF; in lpphy_2062_init()
577 tmp = (((2 * crystalfreq + 1000000 * lpphy->pdiv) / in lpphy_2062_init()
578 (2000000 * lpphy->pdiv)) - 1) & 0xFF; in lpphy_2062_init()
581 ref = (1000 * lpphy->pdiv + 2 * crystalfreq) / (2000 * lpphy->pdiv); in lpphy_2062_init()
2441 tmp2 = lpphy->pdiv * 1000; in lpphy_b2062_tune()
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| D | phy_lp.h | 891 unsigned int pdiv; member
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| /drivers/net/wireless/brcm80211/brcmsmac/phy/ |
| D | phy_int.h | 657 u8 pdiv; member
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