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Searched refs:pipestat (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/gma500/
Dpsb_irq.c88 if ((dev_priv->pipestat[pipe] & mask) != mask) { in psb_enable_pipestat()
90 dev_priv->pipestat[pipe] |= mask; in psb_enable_pipestat()
105 if ((dev_priv->pipestat[pipe] & mask) != 0) { in psb_disable_pipestat()
107 dev_priv->pipestat[pipe] &= ~mask; in psb_disable_pipestat()
131 if (dev_priv->pipestat[pipe] == 0) { in mid_disable_pipe_event()
153 uint32_t pipe_enable = dev_priv->pipestat[pipe]; in mid_pipe_event_handler()
154 uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16; in mid_pipe_event_handler()
Dpsb_drv.c346 dev_priv->pipestat[0] = 0; in psb_driver_load()
347 dev_priv->pipestat[1] = 0; in psb_driver_load()
348 dev_priv->pipestat[2] = 0; in psb_driver_load()
Dpsb_drv.h477 uint32_t pipestat[PSB_NUM_PIPE]; member
/drivers/gpu/drm/i915/
Di915_irq.c319 u32 pipestat; in i9xx_check_fifo_underruns() local
324 pipestat = I915_READ(reg) & 0xffff0000; in i9xx_check_fifo_underruns()
325 if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0) in i9xx_check_fifo_underruns()
328 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); in i9xx_check_fifo_underruns()
343 u32 pipestat = I915_READ(reg) & 0xffff0000; in i9xx_set_fifo_underrun_reporting() local
348 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); in i9xx_set_fifo_underrun_reporting()
351 if (old && pipestat & PIPE_FIFO_UNDERRUN_STATUS) in i9xx_set_fifo_underrun_reporting()
589 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; in __i915_enable_pipestat() local
599 if ((pipestat & enable_mask) == enable_mask) in __i915_enable_pipestat()
605 pipestat |= enable_mask | status_mask; in __i915_enable_pipestat()
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