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Searched refs:ppwr (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/nouveau/core/subdev/pwr/
Dbase.c30 nouveau_pwr_pgob(struct nouveau_pwr *ppwr, bool enable) in nouveau_pwr_pgob() argument
32 const struct nvkm_pwr_impl *impl = (void *)nv_oclass(ppwr); in nouveau_pwr_pgob()
34 impl->pgob(ppwr, enable); in nouveau_pwr_pgob()
38 nouveau_pwr_send(struct nouveau_pwr *ppwr, u32 reply[2], in nouveau_pwr_send() argument
41 struct nouveau_subdev *subdev = nv_subdev(ppwr); in nouveau_pwr_send()
45 addr = nv_rd32(ppwr, 0x10a4a0); in nouveau_pwr_send()
46 if (!nv_wait_ne(ppwr, 0x10a4b0, 0xffffffff, addr ^ 8)) in nouveau_pwr_send()
55 ppwr->recv.message = message; in nouveau_pwr_send()
56 ppwr->recv.process = process; in nouveau_pwr_send()
61 nv_wr32(ppwr, 0x10a580, 0x00000001); in nouveau_pwr_send()
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Dmemx.c7 struct nouveau_pwr *ppwr; member
20 struct nouveau_pwr *ppwr = memx->ppwr; in memx_out() local
24 nv_wr32(ppwr, 0x10a1c4, (memx->c.size << 16) | memx->c.mthd); in memx_out()
26 nv_wr32(ppwr, 0x10a1c4, memx->c.data[i]); in memx_out()
44 nouveau_memx_init(struct nouveau_pwr *ppwr, struct nouveau_memx **pmemx) in nouveau_memx_init() argument
50 ret = ppwr->message(ppwr, reply, PROC_MEMX, MEMX_MSG_INFO, 0, 0); in nouveau_memx_init()
57 memx->ppwr = ppwr; in nouveau_memx_init()
63 nv_wr32(ppwr, 0x10a580, 0x00000003); in nouveau_memx_init()
64 } while (nv_rd32(ppwr, 0x10a580) != 0x00000003); in nouveau_memx_init()
65 nv_wr32(ppwr, 0x10a1c0, 0x01000000 | memx->base); in nouveau_memx_init()
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Dgk104.c32 gk104_pwr_pgob(struct nouveau_pwr *ppwr, bool enable) in gk104_pwr_pgob() argument
34 nv_mask(ppwr, 0x000200, 0x00001000, 0x00000000); in gk104_pwr_pgob()
35 nv_rd32(ppwr, 0x000200); in gk104_pwr_pgob()
36 nv_mask(ppwr, 0x000200, 0x08000000, 0x08000000); in gk104_pwr_pgob()
39 nv_mask(ppwr, 0x10a78c, 0x00000002, 0x00000002); in gk104_pwr_pgob()
40 nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000001); in gk104_pwr_pgob()
41 nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000000); in gk104_pwr_pgob()
43 nv_mask(ppwr, 0x020004, 0xc0000000, enable ? 0xc0000000 : 0x40000000); in gk104_pwr_pgob()
46 nv_mask(ppwr, 0x10a78c, 0x00000002, 0x00000000); in gk104_pwr_pgob()
47 nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000001); in gk104_pwr_pgob()
[all …]
Dnva3.c31 struct nouveau_pwr *ppwr = (void *)object; in nva3_pwr_init() local
32 nv_mask(ppwr, 0x022210, 0x00000001, 0x00000000); in nva3_pwr_init()
33 nv_mask(ppwr, 0x022210, 0x00000001, 0x00000001); in nva3_pwr_init()
34 return nouveau_pwr_init(ppwr); in nva3_pwr_init()
/drivers/gpu/drm/nouveau/core/engine/graph/
Dnve4.c199 struct nouveau_pwr *ppwr = nouveau_pwr(priv); in nve4_graph_init() local
206 if (ppwr) in nve4_graph_init()
207 ppwr->pgob(ppwr, false); in nve4_graph_init()
/drivers/gpu/drm/nouveau/core/subdev/fb/
Dramfuc.h60 struct nouveau_pwr *ppwr = nouveau_pwr(pfb); in ramfuc_init() local
63 ret = nouveau_memx_init(ppwr, &ram->memx); in ramfuc_init()