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Searched refs:pstate (Results 1 – 25 of 25) sorted by relevance

/drivers/gpu/drm/nouveau/core/subdev/clock/
Dbase.c42 u8 pstate, u8 domain, u32 input) in nouveau_clock_adjust() argument
49 data = nvbios_boostEm(bios, pstate, &ver, &hdr, &cnt, &len, &boostE); in nouveau_clock_adjust()
80 struct nouveau_pstate *pstate, int cstatei) in nouveau_cstate_prog() argument
87 if (!list_empty(&pstate->list)) { in nouveau_cstate_prog()
88 cstate = list_entry(pstate->list.prev, typeof(*cstate), head); in nouveau_cstate_prog()
90 cstate = &pstate->base; in nouveau_cstate_prog()
94 ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, +1); in nouveau_cstate_prog()
122 ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, -1); in nouveau_cstate_prog()
139 struct nouveau_pstate *pstate) in nouveau_cstate_new() argument
156 *cstate = pstate->base; in nouveau_cstate_new()
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Dgk20a.c633 gk20a_pstates[i].pstate = i + 1; in gk20a_clock_ctor()
/drivers/cpufreq/
Dintel_pstate.c104 struct pstate_data pstate; member
129 void (*set)(struct cpudata*, int pstate);
244 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); in update_turbo_state()
424 static void byt_set_pstate(struct cpudata *cpudata, int pstate) in byt_set_pstate() argument
430 val = pstate << 8; in byt_set_pstate()
435 int_tofp(pstate - cpudata->pstate.min_pstate), in byt_set_pstate()
441 if (pstate > cpudata->pstate.max_pstate) in byt_set_pstate()
474 int_tofp(cpudata->pstate.max_pstate - in byt_get_vid()
475 cpudata->pstate.min_pstate)); in byt_get_vid()
515 static void core_set_pstate(struct cpudata *cpudata, int pstate) in core_set_pstate() argument
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/drivers/gpu/drm/nouveau/core/engine/device/
Dctrl.c57 args->v0.pstate = clk->pstate; in nouveau_control_mthd_pstate_info()
63 args->v0.pstate = NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN; in nouveau_control_mthd_pstate_info()
78 struct nouveau_pstate *pstate; in nouveau_control_mthd_pstate_attr() local
109 list_for_each_entry(pstate, &clk->states, head) { in nouveau_control_mthd_pstate_attr()
114 lo = pstate->base.domain[domain->name]; in nouveau_control_mthd_pstate_attr()
116 list_for_each_entry(cstate, &pstate->list, head) { in nouveau_control_mthd_pstate_attr()
121 args->v0.state = pstate->pstate; in nouveau_control_mthd_pstate_attr()
/drivers/gpu/drm/nouveau/core/subdev/bios/
Dcstep.c79 info->pstate = (nv_ro16(bios, data + 0x00) & 0x01e0) >> 5; in nvbios_cstepEp()
86 nvbios_cstepEm(struct nouveau_bios *bios, u8 pstate, u8 *ver, u8 *hdr, in nvbios_cstepEm() argument
91 if (info->pstate == pstate) in nvbios_cstepEm()
Dboost.c82 info->pstate = (nv_ro16(bios, data + 0x00) & 0x01e0) >> 5; in nvbios_boostEp()
90 nvbios_boostEm(struct nouveau_bios *bios, u8 pstate, in nvbios_boostEm() argument
95 if (info->pstate == pstate) in nvbios_boostEm()
Dperf.c101 info->pstate = nv_ro08(bios, perf + 0x00); in nvbios_perfEp()
/drivers/staging/android/fiq_debugger/
Dfiq_debugger_arm64.c41 regs->pc, regs->pstate, mode_name(regs)); in fiq_debugger_dump_pc()
60 regs->pstate, mode_name(regs)); in fiq_debugger_dump_regs_aarch32()
100 regs->pc, regs->pstate, mode_name(regs)); in fiq_debugger_dump_regs_aarch64()
121 u32 pstate = READ_SPECIAL_REG(CurrentEl); in fiq_debugger_dump_allregs() local
122 bool in_el2 = (pstate & PSR_MODE_MASK) >= PSR_MODE_EL2t; in fiq_debugger_dump_allregs()
/drivers/gpu/drm/nouveau/
Dnouveau_sysfs.c31 MODULE_PARM_DESC(pstate, "enable sysfs pstate file, which will be moved in the future");
33 module_param_named(pstate, nouveau_pstate, int, 0400);
101 if (info.pstate == state) in nouveau_sysfs_pstate_get()
157 static DEVICE_ATTR(pstate, S_IRUGO | S_IWUSR,
/drivers/gpu/drm/nouveau/core/include/subdev/bios/
Dcstep.h8 u8 pstate; member
15 u16 nvbios_cstepEm(struct nouveau_bios *, u8 pstate, u8 *ver, u8 *hdr,
Dboost.h7 u8 pstate; member
Dperf.h10 u8 pstate; member
/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_sp.h87 unsigned long *pstate; /* pointer to state buffer */ member
473 unsigned long *pstate; member
1387 unsigned long *pstate, bnx2x_obj_type type,
1394 unsigned long *pstate, bnx2x_obj_type type,
1433 int state, unsigned long *pstate,
1473 int state, unsigned long *pstate,
Dbnx2x_sp.c256 return !!test_bit(o->state, o->pstate); in bnx2x_raw_check_pending()
262 clear_bit(o->state, o->pstate); in bnx2x_raw_clear_pending()
269 set_bit(o->state, o->pstate); in bnx2x_raw_set_pending()
282 unsigned long *pstate) in bnx2x_state_wait() argument
294 if (!test_bit(state, pstate)) { in bnx2x_state_wait()
318 return bnx2x_state_wait(bp, raw->state, raw->pstate); in bnx2x_raw_wait()
1911 unsigned long *pstate, bnx2x_obj_type type) in bnx2x_init_raw_obj() argument
1919 raw->pstate = pstate; in bnx2x_init_raw_obj()
1929 int state, unsigned long *pstate, bnx2x_obj_type type, in bnx2x_init_vlan_mac_common() argument
1947 state, pstate, type); in bnx2x_init_vlan_mac_common()
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Dbnx2x_sriov.c643 ramrod->pstate = &vf->filter_state; in bnx2x_vf_prep_rx_mode()
Dbnx2x_main.c6117 ramrod_param.pstate = &bp->sp_state; in bnx2x_set_q_rx_mode()
/drivers/gpu/drm/nouveau/core/include/subdev/
Dclock.h62 u8 pstate; member
81 int pstate; /* current */ member
/drivers/media/platform/blackfin/
Dppi.c212 struct pinctrl_state *pstate; in ppi_set_params() local
217 pstate = pinctrl_lookup_state(pctrl, in ppi_set_params()
219 if (pinctrl_select_state(pctrl, pstate)) in ppi_set_params()
/drivers/net/ethernet/dec/tulip/
Dtulip_core.c1837 pci_power_t pstate; in tulip_suspend() local
1856 pstate = pci_choose_state(pdev, state); in tulip_suspend()
1857 if (state.event == PM_EVENT_SUSPEND && pstate != PCI_D0) { in tulip_suspend()
1861 rc = pci_enable_wake(pdev, pstate, tp->wolinfo.wolopts); in tulip_suspend()
1865 pci_set_power_state(pdev, pstate); in tulip_suspend()
/drivers/gpu/drm/nouveau/nvif/
Dclass.h286 __s8 pstate; /* out: current pstate index */ member
/drivers/gpu/drm/nouveau/core/include/nvif/
Dclass.h286 __s8 pstate; /* out: current pstate index */ member
/drivers/staging/lustre/lustre/obdclass/
Dcl_object.c456 static const char *pstate[] = { in cl_site_stats_print() local
482 seq_printf(m, "%s: %u ", pstate[i], in cl_site_stats_print()
/drivers/scsi/qla2xxx/
Dqla_attr.c1455 uint32_t pstate; in qla2x00_fw_state_show() local
1458 pstate = qlafx00_fw_state_show(dev, attr, buf); in qla2x00_fw_state_show()
1459 return scnprintf(buf, PAGE_SIZE, "0x%x\n", pstate); in qla2x00_fw_state_show()
/drivers/gpu/drm/radeon/
Dr600_dpm.c1117 rdev->pm.dpm.vce_states[i].pstate = in r600_parse_extended_power_table()
Dradeon.h1519 u8 pstate; member