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Searched refs:rFPGA0_TxGainStage (Results 1 – 12 of 12) sorted by relevance

/drivers/staging/rtl8188eu/hal/
Dbb_cfg.c619 hal_data->PHYRegDef[RF_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; in rtl88e_phy_init_bb_rf_register_definition()
620 hal_data->PHYRegDef[RF_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; in rtl88e_phy_init_bb_rf_register_definition()
621 hal_data->PHYRegDef[RF_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; in rtl88e_phy_init_bb_rf_register_definition()
622 hal_data->PHYRegDef[RF_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; in rtl88e_phy_init_bb_rf_register_definition()
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_phy.c439 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; in rtl8192_InitBBRFRegDef()
440 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; in rtl8192_InitBBRFRegDef()
441 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; in rtl8192_InitBBRFRegDef()
442 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; in rtl8192_InitBBRFRegDef()
593 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, in rtl8192_BB_Config_ParaFile()
677 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, in rtl8192_phy_setTxPower()
Dr8192E_phyreg.h62 #define rFPGA0_TxGainStage 0x80c macro
Dr819xE_phyreg.h47 #define rFPGA0_TxGainStage 0x80c macro
/drivers/staging/rtl8192u/
Dr819xU_phy.c627 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; in rtl8192_InitBBRFRegDef()
628 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; in rtl8192_InitBBRFRegDef()
629 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; in rtl8192_InitBBRFRegDef()
630 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; in rtl8192_InitBBRFRegDef()
830 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC), in rtl8192_BB_Config_ParaFile()
Dr819xU_phyreg.h42 #define rFPGA0_TxGainStage 0x80c macro
/drivers/staging/rtl8723au/hal/
Drtl8723a_phycfg.c491 pHalData->PHYRegDef[RF_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; in phy_InitBBRFRegisterDefinition()
492 pHalData->PHYRegDef[RF_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; in phy_InitBBRFRegisterDefinition()
/drivers/staging/rtl8712/
Drtl871x_mp_phy_regdef.h88 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ macro
Drtl871x_mp.c333 set_bb_reg(pAdapter, rFPGA0_TxGainStage, in r8712_SetTxAGCOffset()
/drivers/staging/rtl8188eu/include/
Drtw_mp_phy_regdef.h110 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ macro
DHal8188EPhyReg.h76 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ macro
/drivers/staging/rtl8723au/include/
DHal8723APhyReg.h60 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ macro