Searched refs:rFPGA0_XB_LSSIParameter (Results 1 – 13 of 13) sorted by relevance
| /drivers/staging/rtl8188eu/hal/ |
| D | bb_cfg.c | 612 hal_data->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; in rtl88e_phy_init_bb_rf_register_definition()
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| D | phy.c | 1234 phy_set_bb_reg(adapt, rFPGA0_XB_LSSIParameter, bMaskDWord, in phy_iq_calibrate()
1342 phy_set_bb_reg(adapt, rFPGA0_XB_LSSIParameter, in phy_iq_calibrate()
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| /drivers/staging/rtl8192u/ |
| D | r819xU_phyreg.h | 57 #define rFPGA0_XB_LSSIParameter 0x844 macro
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| D | r819xU_phy.c | 615 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; in rtl8192_InitBBRFRegDef()
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| /drivers/staging/rtl8192e/rtl8192e/ |
| D | r8192E_phyreg.h | 74 #define rFPGA0_XB_LSSIParameter 0x844 macro
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| D | r819xE_phyreg.h | 61 #define rFPGA0_XB_LSSIParameter 0x844 macro
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| D | r8192E_phy.c | 430 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; in rtl8192_InitBBRFRegDef()
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| /drivers/staging/rtl8712/ |
| D | rtl871x_mp_phy_regdef.h | 100 #define rFPGA0_XB_LSSIParameter 0x844 macro
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| /drivers/staging/rtl8723au/hal/ |
| D | HalDMOutSrc8723A_CE.c | 779 PHY_SetBBReg(pAdapter, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000); in _PHY_IQCalibrate()
867 PHY_SetBBReg(pAdapter, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3); in _PHY_IQCalibrate()
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| D | rtl8723a_phycfg.c | 483 pHalData->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; in phy_InitBBRFRegisterDefinition()
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| /drivers/staging/rtl8188eu/include/ |
| D | rtw_mp_phy_regdef.h | 126 #define rFPGA0_XB_LSSIParameter 0x844 macro
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| D | Hal8188EPhyReg.h | 87 #define rFPGA0_XB_LSSIParameter 0x844 macro
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| /drivers/staging/rtl8723au/include/ |
| D | Hal8723APhyReg.h | 78 #define rFPGA0_XB_LSSIParameter 0x844 macro
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