| /drivers/staging/rtl8723au/hal/ |
| D | usb_halinit.c | 836 PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 1); in phy_SsPwrSwitch92CU()
880 PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 1); in phy_SsPwrSwitch92CU()
940 PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable, in phy_SsPwrSwitch92CU()
952 PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 0); in phy_SsPwrSwitch92CU()
1014 PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable, in phy_SsPwrSwitch92CU()
1025 PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 0); in phy_SsPwrSwitch92CU()
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| D | HalDMOutSrc8723A_CE.c | 735 rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, in _PHY_IQCalibrate()
769 PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); in _PHY_IQCalibrate()
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| D | rtl8723a_phycfg.c | 733 PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskByte0, 0x23); in phy_BB8192C_Config_1T()
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| D | odm.c | 438 (u8) ODM_GetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, 0x0F); in odm_CommonInfoSelfInit23a()
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| /drivers/staging/rtl8192u/ |
| D | r819xU_phyreg.h | 110 #define rOFDM0_TRxPathEnable 0xc04 macro
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| D | r819xU_phy.c | 1124 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3); in rtl8192_SetRFPowerState()
1149 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0); in rtl8192_SetRFPowerState()
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| D | r8192U_dm.c | 2985 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<min_rssi_index, 0x0); // 0xc04[3:0] in dm_rxpath_sel_byrssi()
3014 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<i, 0x1); // 0xc04[3:0] in dm_rxpath_sel_byrssi()
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| /drivers/staging/rtl8192e/rtl8192e/ |
| D | r8192E_phyreg.h | 124 #define rOFDM0_TRxPathEnable 0xc04 macro
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| D | r819xE_phyreg.h | 119 #define rOFDM0_TRxPathEnable 0xc04 macro
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| D | r8192E_phy.c | 1410 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0); in PHY_SetRtl8192eRfOff()
1472 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, in SetRFPowerState8190()
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| D | rtl_dm.c | 2522 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, in dm_rxpath_sel_byrssi()
2549 rOFDM0_TRxPathEnable, 0x1 << i, in dm_rxpath_sel_byrssi()
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| /drivers/staging/rtl8712/ |
| D | rtl871x_mp_phy_regdef.h | 181 #define rOFDM0_TRxPathEnable 0xc04 macro
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| D | rtl871x_mp.c | 482 set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, in r8712_SwitchAntenna()
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| /drivers/staging/rtl8188eu/include/ |
| D | rtw_mp_phy_regdef.h | 201 #define rOFDM0_TRxPathEnable 0xc04 macro
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| D | Hal8188EPhyReg.h | 181 #define rOFDM0_TRxPathEnable 0xc04 macro
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| /drivers/staging/rtl8723au/include/ |
| D | Hal8723APhyReg.h | 158 #define rOFDM0_TRxPathEnable 0xc04 macro
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| /drivers/staging/rtl8188eu/hal/ |
| D | phy.c | 1188 rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, in phy_iq_calibrate()
1222 phy_set_bb_reg(adapt, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); in phy_iq_calibrate()
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