Searched refs:rd_full (Results 1 – 2 of 2) sorted by relevance
221 channel->rd_full = 0; in xillybus_isr()463 channel->rd_full = 0; in xilly_setupchannels()1045 (channel->rd_full || in xillybus_myflush()1062 channel->rd_full = 1; in xillybus_myflush()1110 channel->rd_full = 1; /* in xillybus_myflush()1115 empty = !channel->rd_full; in xillybus_myflush()1129 (!channel->rd_full)); in xillybus_myflush()1133 (!channel->rd_full), in xillybus_myflush()1142 if (channel->rd_full) { in xillybus_myflush()1208 full = channel->rd_full; in xillybus_write()[all …]
79 int rd_full; member