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Searched refs:readl_relaxed (Results 1 – 25 of 161) sorted by relevance

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/drivers/crypto/ux500/cryp/
Dcryp.c38 peripheralid2 = readl_relaxed(&device_data->base->periphId2); in cryp_check()
45 readl_relaxed(&device_data->base->periphId0)) in cryp_check()
47 readl_relaxed(&device_data->base->periphId1)) in cryp_check()
49 readl_relaxed(&device_data->base->periphId3)) in cryp_check()
51 readl_relaxed(&device_data->base->pcellId0)) in cryp_check()
53 readl_relaxed(&device_data->base->pcellId1)) in cryp_check()
55 readl_relaxed(&device_data->base->pcellId2)) in cryp_check()
57 readl_relaxed(&device_data->base->pcellId3))) { in cryp_check()
99 while (readl_relaxed(&device_data->base->sr) != in cryp_flush_inoutfifo()
309 ctx->din = readl_relaxed(&src_reg->din); in cryp_save_device_context()
[all …]
Dcryp_p.h24 writel_relaxed((readl_relaxed(reg_name) | mask), reg_name)
27 writel_relaxed(((readl_relaxed(reg_name) & ~(mask)) |\
31 (readl_relaxed(reg_name) & (val))
34 writel_relaxed(((readl_relaxed(reg) & ~(mask)) | \
/drivers/clk/berlin/
Dberlin2-avpll.c129 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_is_enabled()
141 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_enable()
156 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_disable()
174 reg = readl_relaxed(vco->base + VCO_CTRL1); in berlin2_avpll_vco_recalc_rate()
231 reg = readl_relaxed(ch->base + VCO_CTRL10); in berlin2_avpll_channel_is_enabled()
242 reg = readl_relaxed(ch->base + VCO_CTRL10); in berlin2_avpll_channel_enable()
254 reg = readl_relaxed(ch->base + VCO_CTRL10); in berlin2_avpll_channel_disable()
269 reg = readl_relaxed(ch->base + VCO_CTRL30); in berlin2_avpll_channel_recalc_rate()
278 reg = readl_relaxed(ch->base + VCO_SYNC1n(ch->index)); in berlin2_avpll_channel_recalc_rate()
284 reg = readl_relaxed(ch->base + VCO_SYNC2n(ch->index)); in berlin2_avpll_channel_recalc_rate()
[all …]
Dberlin2-div.c84 reg = readl_relaxed(div->base + map->gate_offs); in berlin2_div_is_enabled()
102 reg = readl_relaxed(div->base + map->gate_offs); in berlin2_div_enable()
121 reg = readl_relaxed(div->base + map->gate_offs); in berlin2_div_disable()
139 reg = readl_relaxed(div->base + map->pll_switch_offs); in berlin2_div_set_parent()
148 reg = readl_relaxed(div->base + map->pll_select_offs); in berlin2_div_set_parent()
171 reg = readl_relaxed(div->base + map->pll_switch_offs); in berlin2_div_get_parent()
174 reg = readl_relaxed(div->base + map->pll_select_offs); in berlin2_div_get_parent()
196 divsw = readl_relaxed(div->base + map->div_switch_offs) & in berlin2_div_recalc_rate()
198 div3sw = readl_relaxed(div->base + map->div3_switch_offs) & in berlin2_div_recalc_rate()
210 reg = readl_relaxed(div->base + map->div_select_offs); in berlin2_div_recalc_rate()
/drivers/gpio/
Dgpio-mvebu.c191 u = readl_relaxed(mvebu_gpioreg_out(mvchip)); in mvebu_gpio_set()
206 if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin)) { in mvebu_gpio_get()
207 u = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) ^ in mvebu_gpio_get()
208 readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); in mvebu_gpio_get()
210 u = readl_relaxed(mvebu_gpioreg_out(mvchip)); in mvebu_gpio_get()
224 u = readl_relaxed(mvebu_gpioreg_blink(mvchip)); in mvebu_gpio_blink()
248 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); in mvebu_gpio_direction_input()
275 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); in mvebu_gpio_direction_output()
396 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin); in mvebu_gpio_irq_set_type()
416 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); in mvebu_gpio_irq_set_type()
[all …]
Dgpio-omap.c109 l = readl_relaxed(reg); in omap_set_gpio_direction()
145 l = readl_relaxed(reg); in omap_set_gpio_dataout_mask()
158 return (readl_relaxed(reg) & (BIT(offset))) != 0; in omap_get_gpio_datain()
165 return (readl_relaxed(reg) & (BIT(offset))) != 0; in omap_get_gpio_dataout()
170 int l = readl_relaxed(base + reg); in omap_gpio_rmw()
239 val = readl_relaxed(reg); in omap2_set_gpio_debounce()
314 readl_relaxed(bank->base + bank->regs->leveldetect0); in omap_set_gpio_trigger()
316 readl_relaxed(bank->base + bank->regs->leveldetect1); in omap_set_gpio_trigger()
318 readl_relaxed(bank->base + bank->regs->risingdetect); in omap_set_gpio_trigger()
320 readl_relaxed(bank->base + bank->regs->fallingdetect); in omap_set_gpio_trigger()
[all …]
Dgpio-pxa.c191 gpdr = readl_relaxed(base + GPDR_OFFSET); in __gpio_is_occupied()
197 gafr = readl_relaxed(base + GAFR_OFFSET); in __gpio_is_occupied()
231 value = readl_relaxed(base + GPDR_OFFSET); in pxa_gpio_direction_input()
253 tmp = readl_relaxed(base + GPDR_OFFSET); in pxa_gpio_direction_output()
266 u32 gplr = readl_relaxed(gpio_chip_base(chip) + GPLR_OFFSET); in pxa_gpio_get()
342 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask; in update_edge_detect()
343 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask; in update_edge_detect()
371 gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); in pxa_gpio_irq_type()
410 gedr = readl_relaxed(c->regbase + GEDR_OFFSET); in pxa_gpio_demux_handler()
441 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio); in pxa_mask_muxed_gpio()
[all …]
/drivers/mmc/host/
Dsdhci-msm.c67 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) & in msm_dll_poll_ck_out_en()
78 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) & in msm_dll_poll_ck_out_en()
98 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); in msm_config_cm_dll_phase()
112 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); in msm_config_cm_dll_phase()
118 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) in msm_config_cm_dll_phase()
126 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); in msm_config_cm_dll_phase()
274 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); in msm_cm_dll_set_freq()
294 writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) in msm_init_cm_dll()
298 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) in msm_init_cm_dll()
302 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) in msm_init_cm_dll()
[all …]
/drivers/watchdog/
Domap_wdt.c69 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08) in omap_wdt_reload()
76 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08) in omap_wdt_reload()
87 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10) in omap_wdt_enable()
91 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10) in omap_wdt_enable()
101 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10) in omap_wdt_disable()
105 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10) in omap_wdt_disable()
116 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04) in omap_wdt_set_timer()
120 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04) in omap_wdt_set_timer()
143 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01) in omap_wdt_start()
147 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01) in omap_wdt_start()
[all …]
Dsa1100_wdt.c57 writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3); in sa1100dog_open()
60 writel_relaxed(readl_relaxed(OIER) | OIER_E3, OIER); in sa1100dog_open()
83 writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3); in sa1100dog_write()
117 writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3); in sa1100dog_ioctl()
132 writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3); in sa1100dog_ioctl()
/drivers/phy/
Dphy-qcom-ipq806x-sata.c67 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM3); in qcom_ipq806x_sata_phy_init()
71 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM0) & in qcom_ipq806x_sata_phy_init()
78 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM1) & in qcom_ipq806x_sata_phy_init()
87 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM2) & in qcom_ipq806x_sata_phy_init()
93 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4); in qcom_ipq806x_sata_phy_init()
98 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4); in qcom_ipq806x_sata_phy_init()
109 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4); in qcom_ipq806x_sata_phy_init()
122 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4); in qcom_ipq806x_sata_phy_exit()
/drivers/clocksource/
Dtimer-prima2.c64 WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) & in sirfsoc_timer_interrupt()
83 cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI); in sirfsoc_timer_read()
85 readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO); in sirfsoc_timer_read()
97 now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO); in sirfsoc_timer_set_next_event()
102 now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO); in sirfsoc_timer_set_next_event()
110 u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN); in sirfsoc_timer_set_mode()
138 readl_relaxed(sirfsoc_timer_base + in sirfsoc_clocksource_suspend()
Dtimer-marco.c59 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7, in sirfsoc_timer_count_disable()
66 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x3, in sirfsoc_timer_count_enable()
92 writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | in sirfsoc_timer_read()
95 cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI); in sirfsoc_timer_read()
96 cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO); in sirfsoc_timer_read()
139 sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); in sirfsoc_clocksource_suspend()
154 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | in sirfsoc_clocksource_resume()
283 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | in sirfsoc_marco_timer_init()
Dexynos_mct.c147 if (readl_relaxed(reg_base + stat_addr) & mask) { in exynos4_mct_write()
160 reg = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); in exynos4_mct_frc_start()
178 u32 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U); in exynos4_read_count_64()
182 lo = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L); in exynos4_read_count_64()
183 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U); in exynos4_read_count_64()
199 return readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L); in exynos4_read_count_32()
253 tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); in exynos4_mct_comp0_stop()
266 tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); in exynos4_mct_comp0_start()
355 tmp = readl_relaxed(reg_base + offset); in exynos4_mct_tick_stop()
377 tmp = readl_relaxed(reg_base + mevt->base + MCT_L_TCON_OFFSET); in exynos4_mct_tick_start()
[all …]
/drivers/thermal/
Ddove_thermal.c57 reg = readl_relaxed(priv->control); in dove_init_sensor()
73 reg = readl_relaxed(priv->control); in dove_init_sensor()
78 reg = readl_relaxed(priv->sensor); in dove_init_sensor()
84 reg = readl_relaxed(priv->sensor); in dove_init_sensor()
102 reg = readl_relaxed(priv->control + PMU_TEMP_DIOD_CTRL1_REG); in dove_get_temp()
114 reg = readl_relaxed(priv->sensor); in dove_get_temp()
Darmada_thermal.c82 reg = readl_relaxed(priv->control); in armadaxp_init_sensor()
92 reg = readl_relaxed(priv->control); in armadaxp_init_sensor()
98 reg = readl_relaxed(priv->sensor); in armadaxp_init_sensor()
108 reg = readl_relaxed(priv->control); in armada370_init_sensor()
156 unsigned long reg = readl_relaxed(priv->control); in armada380_init_sensor()
168 unsigned long reg = readl_relaxed(priv->sensor); in armada_is_valid()
187 reg = readl_relaxed(priv->sensor); in armada_get_temp()
/drivers/bus/
Domap_l3_noc.c92 std_err_main = readl_relaxed(l3_targ_stderr); in l3_handle_target()
99 readl_relaxed(l3_targ_slvofslsb)); in l3_handle_target()
121 masterid = (readl_relaxed(l3_targ_mstaddr) & in l3_handle_target()
132 op_code = readl_relaxed(l3_targ_hdr) & 0x7; in l3_handle_target()
134 m_req_info = readl_relaxed(l3_targ_info) & 0xF; in l3_handle_target()
186 err_reg = readl_relaxed(base + flag_mux->offset + in l3_interrupt_handler()
213 mask_val = readl_relaxed(mask_reg); in l3_interrupt_handler()
329 mask_val = readl_relaxed(mask_regx); in l3_resume_noirq()
335 mask_val = readl_relaxed(mask_regx); in l3_resume_noirq()
/drivers/mtd/nand/
Datmel_nand_ecc.h115 readl_relaxed((addr) + ATMEL_PMECC_##reg)
124 readl_relaxed((addr) + ATMEL_PMECC_REMx + ((sector) * 0x40) + ((n) * 4))
127 readl_relaxed((addr) + ATMEL_PMERRLOC_##reg)
136 readl_relaxed((addr) + ATMEL_PMERRLOC_SIGMAx + ((n) * 4))
139 readl_relaxed((addr) + ATMEL_PMERRLOC_ELx + ((n) * 4))
/drivers/video/fbdev/mmp/hw/
Dmmp_ctrl.c48 isr = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR); in ctrl_handle_irq()
49 imask = readl_relaxed(ctrl->reg_base + SPU_IRQ_ENA); in ctrl_handle_irq()
53 tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR); in ctrl_handle_irq()
56 } while ((isr = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR)) & imask); in ctrl_handle_irq()
136 tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id)); in dmafetch_set_fmt()
180 tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id)); in dmafetch_onoff()
191 tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path)); in path_enabledisable()
271 tmp = readl_relaxed(ctrl_regs(path) + intf_ctrl(path->id)) & 0x1; in path_set_mode()
279 tmp = readl_relaxed(ctrl_regs(path) + intf_rbswap_ctrl(path->id)) & in path_set_mode()
312 tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path)); in path_set_mode()
[all …]
Dmmp_spi.c68 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
73 isr = readl_relaxed(reg_base + SPU_IRQ_ISR); in lcd_spi_write()
76 isr = readl_relaxed(reg_base + SPU_IRQ_ISR); in lcd_spi_write()
84 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
111 tmp = readl_relaxed(reg_base + SPU_IOPAD_CONTROL); in lcd_spi_setup()
/drivers/i2c/busses/
Di2c-st.c201 writel_relaxed(readl_relaxed(reg) | mask, reg); in st_i2c_set_bits()
206 writel_relaxed(readl_relaxed(reg) & ~mask, reg); in st_i2c_clr_bits()
246 if (readl_relaxed(i2c_dev->base + SSC_STA) & SSC_STA_RIR) in st_i2c_flush_rx_fifo()
249 count = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT) & in st_i2c_flush_rx_fifo()
253 readl_relaxed(i2c_dev->base + SSC_RBUF); in st_i2c_flush_rx_fifo()
345 sta = readl_relaxed(i2c_dev->base + SSC_STA); in st_i2c_wait_free_bus()
382 sta = readl_relaxed(i2c_dev->base + SSC_STA); in st_i2c_wr_fill_tx_fifo()
386 tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT); in st_i2c_wr_fill_tx_fifo()
411 sta = readl_relaxed(i2c_dev->base + SSC_STA); in st_i2c_rd_fill_tx_fifo()
415 tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT); in st_i2c_rd_fill_tx_fifo()
[all …]
/drivers/char/hw_random/
Dmsm-rng.c58 val = readl_relaxed(rng->base + PRNG_CONFIG); in msm_rng_enable()
62 val = readl_relaxed(rng->base + PRNG_LFSR_CFG); in msm_rng_enable()
67 val = readl_relaxed(rng->base + PRNG_CONFIG); in msm_rng_enable()
71 val = readl_relaxed(rng->base + PRNG_CONFIG); in msm_rng_enable()
103 val = readl_relaxed(rng->base + PRNG_STATUS); in msm_rng_read()
107 val = readl_relaxed(rng->base + PRNG_DATA_OUT); in msm_rng_read()
/drivers/irqchip/
Dirq-sirfsoc.c55 irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID); in sirfsoc_handle_irq()
97 sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0); in sirfsoc_irq_suspend()
98 sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1); in sirfsoc_irq_suspend()
99 sirfsoc_irq_st.level0 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL0); in sirfsoc_irq_suspend()
100 sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1); in sirfsoc_irq_suspend()
/drivers/media/rc/
Dir-hix5hd2.c23 #ifndef readl_relaxed
24 # define readl_relaxed readl macro
103 while (readl_relaxed(priv->base + IR_BUSY)) { in hix5hd2_ir_config()
150 irq_sr = readl_relaxed(priv->base + IR_INTS); in hix5hd2_ir_rx_interrupt()
158 symb_num = readl_relaxed(priv->base + IR_DATAH); in hix5hd2_ir_rx_interrupt()
160 readl_relaxed(priv->base + IR_DATAL); in hix5hd2_ir_rx_interrupt()
170 symb_num = readl_relaxed(priv->base + IR_DATAH); in hix5hd2_ir_rx_interrupt()
172 symb_val = readl_relaxed(priv->base + IR_DATAL); in hix5hd2_ir_rx_interrupt()
/drivers/clk/mmp/
Dclk-apbc.c49 data = readl_relaxed(apbc->base); in clk_apbc_prepare()
63 data = readl_relaxed(apbc->base); in clk_apbc_prepare()
76 data = readl_relaxed(apbc->base); in clk_apbc_prepare()
96 data = readl_relaxed(apbc->base); in clk_apbc_unprepare()
110 data = readl_relaxed(apbc->base); in clk_apbc_unprepare()

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