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Searched refs:regp (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/nouveau/dispnv04/
Dhw.c391 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; in nv_save_state_ramdac() local
395 regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC); in nv_save_state_ramdac()
397 nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, &regp->pllvals); in nv_save_state_ramdac()
402 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11); in nv_save_state_ramdac()
404 regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL); in nv_save_state_ramdac()
407 regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630); in nv_save_state_ramdac()
409 regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634); in nv_save_state_ramdac()
411 regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP); in nv_save_state_ramdac()
412 regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL); in nv_save_state_ramdac()
413 regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW); in nv_save_state_ramdac()
[all …]
Dcrtc.c60 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_set_digital_vibrance() local
62 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level; in nv_crtc_set_digital_vibrance()
64 regp->CRTC[NV_CIO_CRE_CSB] = 0x80; in nv_crtc_set_digital_vibrance()
65 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2; in nv_crtc_set_digital_vibrance()
66 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B); in nv_crtc_set_digital_vibrance()
68 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB); in nv_crtc_set_digital_vibrance()
75 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_set_image_sharpening() local
80 regp->ramdac_634 = level; in nv_crtc_set_image_sharpening()
81 NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634); in nv_crtc_set_image_sharpening()
118 struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index]; in nv_crtc_calc_state_ext() local
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Ddfp.c287 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv04_dfp_mode_set() local
299 regp->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1; in nv04_dfp_mode_set()
300 regp->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1; in nv04_dfp_mode_set()
304 regp->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay; in nv04_dfp_mode_set()
306 regp->fp_horiz_regs[FP_CRTC] = output_mode->hsync_start - drm->vbios.digital_min_front_porch - 1; in nv04_dfp_mode_set()
307 regp->fp_horiz_regs[FP_SYNC_START] = output_mode->hsync_start - 1; in nv04_dfp_mode_set()
308 regp->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1; in nv04_dfp_mode_set()
309 regp->fp_horiz_regs[FP_VALID_START] = output_mode->hskew; in nv04_dfp_mode_set()
310 regp->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - 1; in nv04_dfp_mode_set()
312 regp->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1; in nv04_dfp_mode_set()
[all …]
Dcursor.c42 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv04_cursor_set_offset() local
45 regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = in nv04_cursor_set_offset()
48 regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = in nv04_cursor_set_offset()
51 regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |= in nv04_cursor_set_offset()
53 regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = offset >> 24; in nv04_cursor_set_offset()
55 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); in nv04_cursor_set_offset()
56 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); in nv04_cursor_set_offset()
57 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); in nv04_cursor_set_offset()
Dtvnv04.c143 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv04_tv_mode_set() local
145 regp->tv_htotal = adjusted_mode->htotal; in nv04_tv_mode_set()
146 regp->tv_vtotal = adjusted_mode->vtotal; in nv04_tv_mode_set()
152 regp->tv_hskew = 1; in nv04_tv_mode_set()
153 regp->tv_hsync_delay = 1; in nv04_tv_mode_set()
154 regp->tv_hsync_delay2 = 64; in nv04_tv_mode_set()
155 regp->tv_vskew = 1; in nv04_tv_mode_set()
156 regp->tv_vsync_delay = 1; in nv04_tv_mode_set()
/drivers/video/fbdev/
Dcg3.c335 u8 __iomem *regp = &((u8 __iomem *)par->regs)[p[0]]; in cg3_do_default_mode() local
336 sbus_writeb(p[1], regp); in cg3_do_default_mode()
339 u8 __iomem *regp; in cg3_do_default_mode() local
341 regp = (u8 __iomem *)&par->regs->cmap.addr; in cg3_do_default_mode()
342 sbus_writeb(p[0], regp); in cg3_do_default_mode()
343 regp = (u8 __iomem *)&par->regs->cmap.control; in cg3_do_default_mode()
344 sbus_writeb(p[1], regp); in cg3_do_default_mode()
Dbw2.c269 u8 __iomem *regp = &((u8 __iomem *)par->regs)[p[0]]; in bw2_do_default_mode() local
270 sbus_writeb(p[1], regp); in bw2_do_default_mode()
/drivers/mfd/
Dab3100-core.c493 int regp; in ab3100_get_set_reg() local
512 regp = i; in ab3100_get_set_reg()
523 err = kstrtou8(&buf[regp], 16, &user_reg); in ab3100_get_set_reg()
/drivers/gpu/drm/nouveau/core/engine/fifo/
Dnv04.h140 unsigned regp; member
Dnv04.c224 u32 rv = (nv_rd32(priv, c->regp) & rm) >> c->regs; in nv04_fifo_chan_fini()
231 nv_wr32(priv, c->regp, 0x00000000); in nv04_fifo_chan_fini()
/drivers/net/ethernet/amd/
Datarilance.c406 static noinline int __init addr_accessible(volatile void *regp, int wordflag, in addr_accessible() argument
445 : "a" (regp), "a" (&vbr[2]), "rm" (wordflag), "rm" (writeflag) in addr_accessible()
/drivers/hwmon/
Dnct6775.c3243 static void add_temp_sensors(struct nct6775_data *data, const u16 *regp, in add_temp_sensors() argument
3252 if (!regp[i]) in add_temp_sensors()
3254 src = nct6775_read_value(data, regp[i]); in add_temp_sensors()