| /drivers/gpu/host1x/hw/ |
| D | hw_host1x02_uclass.h | 60 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f() argument
62 return (v & 0xff) << 8; in host1x_uclass_incr_syncpt_cond_f()
64 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
65 host1x_uclass_incr_syncpt_cond_f(v)
66 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f() argument
68 return (v & 0xff) << 0; in host1x_uclass_incr_syncpt_indx_f()
70 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
71 host1x_uclass_incr_syncpt_indx_f(v)
78 static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v) in host1x_uclass_wait_syncpt_indx_f() argument
80 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_indx_f()
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| D | hw_host1x01_uclass.h | 60 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f() argument
62 return (v & 0xff) << 8; in host1x_uclass_incr_syncpt_cond_f()
64 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
65 host1x_uclass_incr_syncpt_cond_f(v)
66 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f() argument
68 return (v & 0xff) << 0; in host1x_uclass_incr_syncpt_indx_f()
70 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
71 host1x_uclass_incr_syncpt_indx_f(v)
78 static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v) in host1x_uclass_wait_syncpt_indx_f() argument
80 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_indx_f()
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| D | hw_host1x04_uclass.h | 60 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f() argument
62 return (v & 0xff) << 8; in host1x_uclass_incr_syncpt_cond_f()
64 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
65 host1x_uclass_incr_syncpt_cond_f(v)
66 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f() argument
68 return (v & 0xff) << 0; in host1x_uclass_incr_syncpt_indx_f()
70 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
71 host1x_uclass_incr_syncpt_indx_f(v)
78 static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v) in host1x_uclass_wait_syncpt_indx_f() argument
80 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_indx_f()
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| /drivers/md/ |
| D | dm-verity-target.c | 44 struct dm_verity *v; member
78 static sector_t verity_map_sector(struct dm_verity *v, sector_t bi_sector) in verity_map_sector() argument
80 return v->data_start + dm_target_offset(v->ti, bi_sector); in verity_map_sector()
89 static sector_t verity_position_at_level(struct dm_verity *v, sector_t block, in verity_position_at_level() argument
92 return block >> (level * v->hash_per_block_bits); in verity_position_at_level()
98 static int verity_hash_init(struct dm_verity *v, struct shash_desc *desc) in verity_hash_init() argument
102 desc->tfm = v->tfm; in verity_hash_init()
112 if (likely(v->version >= 1)) { in verity_hash_init()
113 r = crypto_shash_update(desc, v->salt, v->salt_size); in verity_hash_init()
124 static int verity_hash_update(struct dm_verity *v, struct shash_desc *desc, in verity_hash_update() argument
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| D | dm-verity-fec.c | 21 bool verity_fec_is_enabled(struct dm_verity *v) in verity_fec_is_enabled() argument
23 return v->fec && v->fec->dev; in verity_fec_is_enabled()
32 return (struct dm_verity_fec_io *) verity_io_digest_end(io->v, io); in fec_io()
38 static inline u64 fec_interleave(struct dm_verity *v, u64 offset) in fec_interleave() argument
42 mod = do_div(offset, v->fec->rsn); in fec_interleave()
43 return offset + mod * (v->fec->rounds << v->data_dev_block_bits); in fec_interleave()
49 static int fec_decode_rs8(struct dm_verity *v, struct dm_verity_fec_io *fio, in fec_decode_rs8() argument
55 for (i = 0; i < v->fec->roots; i++) in fec_decode_rs8()
58 return decode_rs8(fio->rs, data, par, v->fec->rsn, NULL, neras, in fec_decode_rs8()
66 static u8 *fec_read_parity(struct dm_verity *v, u64 rsb, int index, in fec_read_parity() argument
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| /drivers/isdn/i4l/ |
| D | isdn_v110.c | 93 isdn_v110_stream *v; in isdn_v110_open() local
95 if ((v = kzalloc(sizeof(isdn_v110_stream), GFP_ATOMIC)) == NULL) in isdn_v110_open()
97 v->key = key; in isdn_v110_open()
98 v->nbits = 0; in isdn_v110_open()
100 v->nbits++; in isdn_v110_open()
102 v->nbytes = 8 / v->nbits; in isdn_v110_open()
103 v->decodelen = 0; in isdn_v110_open()
107 v->OnlineFrame = V110_OnMatrix_38400; in isdn_v110_open()
108 v->OfflineFrame = V110_OffMatrix_38400; in isdn_v110_open()
111 v->OnlineFrame = V110_OnMatrix_19200; in isdn_v110_open()
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| /drivers/iommu/ |
| D | msm_iommu_hw-8xxx.h | 33 #define SET_GLOBAL_REG_N(b, n, r, v) SET_GLOBAL_REG(b, ((r) + (n << 2)), (v)) argument
41 #define SET_GLOBAL_FIELD(b, r, F, v) \ argument
42 SET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT, (v))
43 #define SET_CONTEXT_FIELD(b, c, r, F, v) \ argument
44 SET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT, (v))
48 #define SET_FIELD(addr, mask, shift, v) \ argument
51 writel((t & ~((mask) << (shift))) + (((v) & (mask)) << (shift)), addr);\
97 #define SET_M2VCBR_N(b, N, v) SET_GLOBAL_REG_N(M2VCBR_N, N, (b), (v)) argument
98 #define SET_CBACR_N(b, N, v) SET_GLOBAL_REG_N(CBACR_N, N, (b), (v)) argument
99 #define SET_TLBRSW(b, v) SET_GLOBAL_REG(TLBRSW, (b), (v)) argument
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| /drivers/target/sbp/ |
| D | sbp_target.h | 18 #define ORB_NOTIFY(v) (((v) >> 31) & 0x01) argument
19 #define ORB_REQUEST_FORMAT(v) (((v) >> 29) & 0x03) argument
21 #define MANAGEMENT_ORB_FUNCTION(v) (((v) >> 16) & 0x0f) argument
33 #define LOGIN_ORB_EXCLUSIVE(v) (((v) >> 28) & 0x01) argument
34 #define LOGIN_ORB_RESERVED(v) (((v) >> 24) & 0x0f) argument
35 #define LOGIN_ORB_RECONNECT(v) (((v) >> 20) & 0x0f) argument
36 #define LOGIN_ORB_LUN(v) (((v) >> 0) & 0xffff) argument
37 #define LOGIN_ORB_PASSWORD_LENGTH(v) (((v) >> 16) & 0xffff) argument
38 #define LOGIN_ORB_RESPONSE_LENGTH(v) (((v) >> 0) & 0xffff) argument
40 #define RECONNECT_ORB_LOGIN_ID(v) (((v) >> 0) & 0xffff) argument
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| /drivers/net/ethernet/altera/ |
| D | altera_tse.h | 63 #define GET_BIT_VALUE(v, bit) (((v) >> (bit)) & 0x1) argument
83 #define MAC_CMDCFG_TX_ADDR_SEL(v) (((v) & 0x7) << 16) argument
95 #define MAC_CMDCFG_TX_ENA_GET(v) GET_BIT_VALUE(v, 0) argument
96 #define MAC_CMDCFG_RX_ENA_GET(v) GET_BIT_VALUE(v, 1) argument
97 #define MAC_CMDCFG_XON_GEN_GET(v) GET_BIT_VALUE(v, 2) argument
98 #define MAC_CMDCFG_ETH_SPEED_GET(v) GET_BIT_VALUE(v, 3) argument
99 #define MAC_CMDCFG_PROMIS_EN_GET(v) GET_BIT_VALUE(v, 4) argument
100 #define MAC_CMDCFG_PAD_EN_GET(v) GET_BIT_VALUE(v, 5) argument
101 #define MAC_CMDCFG_CRC_FWD_GET(v) GET_BIT_VALUE(v, 6) argument
102 #define MAC_CMDCFG_PAUSE_FWD_GET(v) GET_BIT_VALUE(v, 7) argument
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| D | altera_msgdmahw.h | 120 #define MSGDMA_CSR_STAT_BUSY_GET(v) GET_BIT_VALUE(v, 0) argument
121 #define MSGDMA_CSR_STAT_DESC_BUF_EMPTY_GET(v) GET_BIT_VALUE(v, 1) argument
122 #define MSGDMA_CSR_STAT_DESC_BUF_FULL_GET(v) GET_BIT_VALUE(v, 2) argument
123 #define MSGDMA_CSR_STAT_RESP_BUF_EMPTY_GET(v) GET_BIT_VALUE(v, 3) argument
124 #define MSGDMA_CSR_STAT_RESP_BUF_FULL_GET(v) GET_BIT_VALUE(v, 4) argument
125 #define MSGDMA_CSR_STAT_STOPPED_GET(v) GET_BIT_VALUE(v, 5) argument
126 #define MSGDMA_CSR_STAT_RESETTING_GET(v) GET_BIT_VALUE(v, 6) argument
127 #define MSGDMA_CSR_STAT_STOPPED_ON_ERR_GET(v) GET_BIT_VALUE(v, 7) argument
128 #define MSGDMA_CSR_STAT_STOPPED_ON_EARLY_GET(v) GET_BIT_VALUE(v, 8) argument
129 #define MSGDMA_CSR_STAT_IRQ_GET(v) GET_BIT_VALUE(v, 9) argument
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| /drivers/mtd/nand/gpmi-nand/ |
| D | gpmi-regs.h | 31 #define BF_GPMI_CTRL0_COMMAND_MODE(v) \ argument
32 (((v) << BP_GPMI_CTRL0_COMMAND_MODE) & BM_GPMI_CTRL0_COMMAND_MODE)
50 #define BF_GPMI_CTRL0_LOCK_CS(v, x) 0x0 argument
56 #define BF_GPMI_CTRL0_CS(v, x) (((v) << BP_GPMI_CTRL0_CS) & \ argument
63 #define BF_GPMI_CTRL0_ADDRESS(v) \ argument
64 (((v) << BP_GPMI_CTRL0_ADDRESS) & BM_GPMI_CTRL0_ADDRESS)
75 #define BF_GPMI_CTRL0_XFER_COUNT(v) \ argument
76 (((v) << BP_GPMI_CTRL0_XFER_COUNT) & BM_GPMI_CTRL0_XFER_COUNT)
87 #define BF_GPMI_ECCCTRL_ECC_CMD(v) \ argument
88 (((v) << BP_GPMI_ECCCTRL_ECC_CMD) & BM_GPMI_ECCCTRL_ECC_CMD)
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| D | bch-regs.h | 43 #define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) \ argument
44 (((v) << BP_BCH_FLASH0LAYOUT0_NBLOCKS) & BM_BCH_FLASH0LAYOUT0_NBLOCKS)
48 #define BF_BCH_FLASH0LAYOUT0_META_SIZE(v) \ argument
49 (((v) << BP_BCH_FLASH0LAYOUT0_META_SIZE)\
56 #define BF_BCH_FLASH0LAYOUT0_ECC0(v, x) \ argument
58 ? (((v) << MX6Q_BP_BCH_FLASH0LAYOUT0_ECC0) \
60 : (((v) << BP_BCH_FLASH0LAYOUT0_ECC0) \
67 #define BF_BCH_FLASH0LAYOUT0_GF(v, x) \ argument
68 ((GPMI_IS_MX6(x) && ((v) == 14)) \
79 #define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v, x) \ argument
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| /drivers/staging/comedi/drivers/ |
| D | s626.h | 504 #define S626_UNMAKE(v, w, p) (((v) >> (p)) & ((1 << (w)) - 1)) argument
560 #define S626_GET_CRA_INDXSRC_B(v) \ argument
561 S626_UNMAKE((v), S626_CRAWID_INDXSRC_B, S626_CRABIT_INDXSRC_B)
562 #define S626_GET_CRA_CNTSRC_B(v) \ argument
563 S626_UNMAKE((v), S626_CRAWID_CNTSRC_B, S626_CRABIT_CNTSRC_B)
564 #define S626_GET_CRA_INDXPOL_A(v) \ argument
565 S626_UNMAKE((v), S626_CRAWID_INDXPOL_A, S626_CRABIT_INDXPOL_A)
566 #define S626_GET_CRA_LOADSRC_A(v) \ argument
567 S626_UNMAKE((v), S626_CRAWID_LOADSRC_A, S626_CRABIT_LOADSRC_A)
568 #define S626_GET_CRA_CLKMULT_A(v) \ argument
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| /drivers/media/pci/cx18/ |
| D | cx18-av-audio.c | 306 u8 v; in cx18_av_audio_set_path() local
309 v = cx18_av_read(cx, 0x803) & ~0x10; in cx18_av_audio_set_path()
310 cx18_av_write_expect(cx, 0x803, v, v, 0x1f); in cx18_av_audio_set_path()
313 v = cx18_av_read(cx, 0x810) | 0x01; in cx18_av_audio_set_path()
314 cx18_av_write_expect(cx, 0x810, v, v, 0x0f); in cx18_av_audio_set_path()
334 v = cx18_av_read(cx, 0x810) & ~0x01; in cx18_av_audio_set_path()
335 cx18_av_write_expect(cx, 0x810, v, v, 0x0f); in cx18_av_audio_set_path()
340 v = cx18_av_read(cx, 0x803) | 0x10; in cx18_av_audio_set_path()
341 cx18_av_write_expect(cx, 0x803, v, v, 0x1f); in cx18_av_audio_set_path()
392 u8 v; in set_mute() local
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| D | cx18-av-firmware.c | 83 u32 u, v; in cx18_av_loadfw() local
186 v = cx18_read_reg(cx, CX18_AUDIO_ENABLE); in cx18_av_loadfw()
188 if (v & 0x800) in cx18_av_loadfw()
189 cx18_write_reg_expect(cx, v & 0xFFFFFBFF, CX18_AUDIO_ENABLE, in cx18_av_loadfw()
193 v = cx18_read_reg(cx, CX18_AUDIO_ENABLE); in cx18_av_loadfw()
194 u = v & CX18_AI1_MUX_MASK; in cx18_av_loadfw()
195 v &= ~CX18_AI1_MUX_MASK; in cx18_av_loadfw()
198 v |= CX18_AI1_MUX_I2S1; in cx18_av_loadfw()
199 cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE, in cx18_av_loadfw()
200 v, CX18_AI1_MUX_MASK); in cx18_av_loadfw()
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| /drivers/usb/musb/ |
| D | tusb6010.h | 54 #define TUSB_PHY_OTG_CTRL_PHYREF_CLKSEL(v) (((v) & 3) << 7) argument
78 # define TUSB_DEV_OTG_TIMER_VAL(v) ((v) & 0x07ffffff) argument
84 #define TUSB_PRCM_CONF_SYS_CLKSEL(v) (((v) & 3) << 16) argument
88 #define TUSB_PRCM_MNGMT_SRP_FIX_TIMER(v) (((v) & 0xf) << 25) argument
90 #define TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(v) (((v) & 0xf) << 20) argument
197 #define TUSB_INT_CTRL_CONF_INT_RELCYC(v) (((v) & 0x7) << 18) argument
200 #define TUSB_GPIO_CONF_DMAREQ(v) (((v) & 0x3f) << 24) argument
201 #define TUSB_DMA_REQ_CONF_BURST_SIZE(v) (((v) & 3) << 26) argument
202 #define TUSB_DMA_REQ_CONF_DMA_REQ_EN(v) (((v) & 0x3f) << 20) argument
203 #define TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(v) (((v) & 0xf) << 16) argument
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| /drivers/bcma/ |
| D | driver_pci.c | 36 u32 v; in bcma_pcie_mdio_set_phy() local
39 v = BCMA_CORE_PCI_MDIODATA_START; in bcma_pcie_mdio_set_phy()
40 v |= BCMA_CORE_PCI_MDIODATA_WRITE; in bcma_pcie_mdio_set_phy()
41 v |= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR << in bcma_pcie_mdio_set_phy()
43 v |= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR << in bcma_pcie_mdio_set_phy()
45 v |= BCMA_CORE_PCI_MDIODATA_TA; in bcma_pcie_mdio_set_phy()
46 v |= (phy << 4); in bcma_pcie_mdio_set_phy()
47 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v); in bcma_pcie_mdio_set_phy()
51 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL); in bcma_pcie_mdio_set_phy()
52 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) in bcma_pcie_mdio_set_phy()
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| /drivers/media/v4l2-core/ |
| D | v4l2-of.c | 30 u32 v; in v4l2_of_parse_csi_bus() local
47 if (!of_property_read_u32(node, "clock-lanes", &v)) { in v4l2_of_parse_csi_bus()
48 bus->clock_lane = v; in v4l2_of_parse_csi_bus()
52 if (of_get_property(node, "clock-noncontinuous", &v)) in v4l2_of_parse_csi_bus()
66 u32 v; in v4l2_of_parse_parallel_bus() local
68 if (!of_property_read_u32(node, "hsync-active", &v)) in v4l2_of_parse_parallel_bus()
69 flags |= v ? V4L2_MBUS_HSYNC_ACTIVE_HIGH : in v4l2_of_parse_parallel_bus()
72 if (!of_property_read_u32(node, "vsync-active", &v)) in v4l2_of_parse_parallel_bus()
73 flags |= v ? V4L2_MBUS_VSYNC_ACTIVE_HIGH : in v4l2_of_parse_parallel_bus()
76 if (!of_property_read_u32(node, "pclk-sample", &v)) in v4l2_of_parse_parallel_bus()
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| /drivers/tty/serial/ |
| D | bfin_sport_uart.h | 62 #define SPORT_PUT_TCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR1), v) argument
63 #define SPORT_PUT_TCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR2), v) argument
64 #define SPORT_PUT_TCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCLKDIV), v) argument
65 #define SPORT_PUT_TFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TFSDIV), v) argument
66 #define SPORT_PUT_TX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TX), v) argument
67 #define SPORT_PUT_RX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RX), v) argument
68 #define SPORT_PUT_RCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR1), v) argument
69 #define SPORT_PUT_RCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR2), v) argument
70 #define SPORT_PUT_RCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCLKDIV), v) argument
71 #define SPORT_PUT_RFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RFSDIV), v) argument
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| /drivers/clk/ti/ |
| D | apll.c | 44 u32 v; in dra7_apll_enable() local
55 v = ti_clk_ll_ops->clk_readl(ad->idlest_reg); in dra7_apll_enable()
57 if ((v & ad->idlest_mask) == state) in dra7_apll_enable()
60 v = ti_clk_ll_ops->clk_readl(ad->control_reg); in dra7_apll_enable()
61 v &= ~ad->enable_mask; in dra7_apll_enable()
62 v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask); in dra7_apll_enable()
63 ti_clk_ll_ops->clk_writel(v, ad->control_reg); in dra7_apll_enable()
68 v = ti_clk_ll_ops->clk_readl(ad->idlest_reg); in dra7_apll_enable()
69 if ((v & ad->idlest_mask) == state) in dra7_apll_enable()
93 u32 v; in dra7_apll_disable() local
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| /drivers/media/dvb-frontends/ |
| D | mb86a16.c | 754 int v, int R, in swp_info_get() argument
764 crnt_swp_freq = fOSC_start * 1000 + v * swp_ofs; in swp_info_get()
782 static int swp_freq_calcuation(struct mb86a16_state *state, int i, int v, int *V, int vmax, int vm… in swp_freq_calcuation() argument
787 if ((i % 2 == 1) && (v <= vmax)) { in swp_freq_calcuation()
789 if ((v - 1 == vmin) && in swp_freq_calcuation()
790 (*(V + 30 + v) >= 0) && in swp_freq_calcuation()
791 (*(V + 30 + v - 1) >= 0) && in swp_freq_calcuation()
792 (*(V + 30 + v - 1) > *(V + 30 + v)) && in swp_freq_calcuation()
793 (*(V + 30 + v - 1) > SIGMIN)) { in swp_freq_calcuation()
796 *SIG1 = *(V + 30 + v - 1); in swp_freq_calcuation()
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| /drivers/net/ethernet/chelsio/cxgb3/ |
| D | aq100x.c | 97 unsigned int v; in aq100x_intr_clear() local
99 t3_mdio_read(phy, MDIO_MMD_VEND1, AQ_IFLAG_GLOBAL, &v); in aq100x_intr_clear()
100 t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_STAT1, &v); in aq100x_intr_clear()
108 unsigned int cause, v; in aq100x_intr_handler() local
115 t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_STAT1, &v); in aq100x_intr_handler()
211 unsigned int v; in aq100x_get_link_status() local
214 err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AQ_LINK_STAT, &v); in aq100x_get_link_status()
218 *link_ok = v & 1; in aq100x_get_link_status()
223 err = t3_mdio_read(phy, MDIO_MMD_AN, AQ_ANEG_STAT, &v); in aq100x_get_link_status()
228 switch (v & 0x6) { in aq100x_get_link_status()
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| /drivers/gpu/drm/ |
| D | drm_legacy.h | 50 int drm_legacy_resctx(struct drm_device *d, void *v, struct drm_file *f);
51 int drm_legacy_addctx(struct drm_device *d, void *v, struct drm_file *f);
52 int drm_legacy_getctx(struct drm_device *d, void *v, struct drm_file *f);
53 int drm_legacy_switchctx(struct drm_device *d, void *v, struct drm_file *f);
54 int drm_legacy_newctx(struct drm_device *d, void *v, struct drm_file *f);
55 int drm_legacy_rmctx(struct drm_device *d, void *v, struct drm_file *f);
57 int drm_legacy_setsareactx(struct drm_device *d, void *v, struct drm_file *f);
58 int drm_legacy_getsareactx(struct drm_device *d, void *v, struct drm_file *f);
66 int drm_legacy_addmap_ioctl(struct drm_device *d, void *v, struct drm_file *f);
67 int drm_legacy_rmmap_ioctl(struct drm_device *d, void *v, struct drm_file *f);
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| /drivers/rtc/ |
| D | rtc-da9052.c | 61 uint8_t v[5]; in da9052_read_alarm() local
63 ret = da9052_group_read(rtc->da9052, DA9052_ALARM_MI_REG, 5, v); in da9052_read_alarm()
69 rtc_tm->tm_year = (v[4] & DA9052_RTC_YEAR) + 100; in da9052_read_alarm()
70 rtc_tm->tm_mon = (v[3] & DA9052_RTC_MONTH) - 1; in da9052_read_alarm()
71 rtc_tm->tm_mday = v[2] & DA9052_RTC_DAY; in da9052_read_alarm()
72 rtc_tm->tm_hour = v[1] & DA9052_RTC_HOUR; in da9052_read_alarm()
73 rtc_tm->tm_min = v[0] & DA9052_RTC_MIN; in da9052_read_alarm()
84 uint8_t v[3]; in da9052_set_alarm() local
106 v[0] = rtc_tm->tm_hour; in da9052_set_alarm()
107 v[1] = rtc_tm->tm_mday; in da9052_set_alarm()
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| /drivers/scsi/arm/ |
| D | cumana_1.c | 52 #define L(v) (((v)<<16)|((v) & 0x0000ffff)) argument
53 #define H(v) (((v)>>16)|((v) & 0xffff0000)) argument
68 unsigned long v; in NCR5380_pwrite() local
74 v=*laddr++; writew(L(v), dma); writew(H(v), dma); in NCR5380_pwrite()
75 v=*laddr++; writew(L(v), dma); writew(H(v), dma); in NCR5380_pwrite()
76 v=*laddr++; writew(L(v), dma); writew(H(v), dma); in NCR5380_pwrite()
77 v=*laddr++; writew(L(v), dma); writew(H(v), dma); in NCR5380_pwrite()
78 v=*laddr++; writew(L(v), dma); writew(H(v), dma); in NCR5380_pwrite()
79 v=*laddr++; writew(L(v), dma); writew(H(v), dma); in NCR5380_pwrite()
80 v=*laddr++; writew(L(v), dma); writew(H(v), dma); in NCR5380_pwrite()
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