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Searched refs:vlv_dpio_read (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/i915/
Dintel_hdmi.c1213 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); in vlv_hdmi_pre_enable()
1296 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); in chv_hdmi_pre_pll_enable()
1304 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); in chv_hdmi_pre_pll_enable()
1314 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); in chv_hdmi_pre_pll_enable()
1322 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); in chv_hdmi_pre_pll_enable()
1335 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); in chv_hdmi_pre_pll_enable()
1375 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); in chv_hdmi_post_disable()
1379 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); in chv_hdmi_post_disable()
1383 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); in chv_hdmi_post_disable()
1387 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); in chv_hdmi_post_disable()
[all …]
Dintel_dp.c2362 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); in chv_post_disable_dp()
2366 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); in chv_post_disable_dp()
2370 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); in chv_post_disable_dp()
2374 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); in chv_post_disable_dp()
2613 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); in vlv_pre_enable_dp()
2683 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); in chv_pre_enable_dp()
2687 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); in chv_pre_enable_dp()
2691 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); in chv_pre_enable_dp()
2695 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); in chv_pre_enable_dp()
2745 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); in chv_dp_pre_pll_enable()
[all …]
Dintel_sideband.c188 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg) in vlv_dpio_read() function
Dintel_display.c1589 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); in chv_enable_pll()
1756 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); in chv_disable_pll()
1762 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); in chv_disable_pll()
1766 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); in chv_disable_pll()
5622 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); in vlv_pllb_recal_opamp()
5627 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); in vlv_pllb_recal_opamp()
5632 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); in vlv_pllb_recal_opamp()
5636 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); in vlv_pllb_recal_opamp()
5747 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); in vlv_prepare_pll()
5800 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); in vlv_prepare_pll()
[all …]
Di915_drv.h2862 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);