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Searched refs:azx_readl (Results 1 – 3 of 3) sorted by relevance

/sound/pci/hda/
Dhda_controller.c66 azx_readl(chip, INTCTL) | (1 << azx_dev->index)); in azx_stream_start()
88 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index)); in azx_stream_stop()
158 if (!(azx_readl(chip, DPLBASE) & AZX_DPLBASE_ENABLE)) in azx_setup_controller()
225 return azx_readl(chip, WALLCLK); in azx_cc_read()
598 azx_readl(chip, OLD_SSYNC) | sbits); in azx_pcm_trigger()
600 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits); in azx_pcm_trigger()
607 azx_dev->start_wallclk = azx_readl(chip, WALLCLK); in azx_pcm_trigger()
655 azx_readl(chip, OLD_SSYNC) & ~sbits); in azx_pcm_trigger()
657 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits); in azx_pcm_trigger()
1221 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~AZX_GCTL_UNSOL); in azx_rirb_get_response()
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Dhda_priv.h381 #define azx_readl(chip, reg) \ macro
Dhda_intel.c575 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk; in azx_position_ok()