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Searched refs:ieee754sp_zero (Results 1 – 14 of 14) sorted by relevance

/arch/mips/math-emu/
Dsp_simple.c36 y = ieee754sp_sub(ieee754sp_zero(0), x); in ieee754sp_neg()
55 y = ieee754sp_sub(ieee754sp_zero(0), x); in ieee754sp_abs()
57 y = ieee754sp_add(ieee754sp_zero(0), x); in ieee754sp_abs()
Dsp_fdp.c63 return ieee754sp_zero(xs); in ieee754sp_fdp()
72 return ieee754sp_zero(xs); in ieee754sp_fdp()
Dieee754sp.c117 return ieee754sp_zero(sn); in ieee754sp_format()
122 return ieee754sp_zero(1); in ieee754sp_format()
125 return ieee754sp_zero(0); in ieee754sp_format()
Dsp_sub.c95 return ieee754sp_zero(ieee754_csr.rm == FPU_CSR_RD); in ieee754sp_sub()
167 return ieee754sp_zero(1); /* round negative inf. => sign = -1 */ in ieee754sp_sub()
169 return ieee754sp_zero(0); /* other round modes => sign = 1 */ in ieee754sp_sub()
Dsp_div.c81 return ieee754sp_zero(xs ^ ys); in ieee754sp_div()
102 return ieee754sp_zero(xs == ys ? 0 : 1); in ieee754sp_div()
Dsp_fint.c33 return ieee754sp_zero(0); in ieee754sp_fint()
Dsp_flong.c33 return ieee754sp_zero(0); in ieee754sp_flong()
Dsp_add.c95 return ieee754sp_zero(ieee754_csr.rm == FPU_CSR_RD); in ieee754sp_add()
166 return ieee754sp_zero(ieee754_csr.rm == FPU_CSR_RD); in ieee754sp_add()
Dsp_fmax.c85 return ieee754sp_zero(1); in ieee754sp_fmax()
185 return ieee754sp_zero(1); in ieee754sp_fmaxa()
Dsp_fmin.c85 return ieee754sp_zero(1); in ieee754sp_fmin()
185 return ieee754sp_zero(1); in ieee754sp_fmina()
Dsp_mul.c99 return ieee754sp_zero(xs ^ ys); in ieee754sp_mul()
Dieee754int.h145 v = ieee754sp_zero(vs); \
Dsp_maddf.c252 return ieee754sp_zero(ieee754_csr.rm == FPU_CSR_RD); in _sp_maddf()
Dieee754.h256 #define ieee754sp_zero(sn) (ieee754sp_spcvals[IEEE754_SPCVAL_PZERO+(sn)]) macro