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/arch/arm/mach-s3c24xx/
Dcpufreq-utils.c36 unsigned long refresh; in s3c2410_cpufreq_setrefresh() local
46 refresh = (cfg->freq.hclk / 100) * (board->refresh / 10); in s3c2410_cpufreq_setrefresh()
47 refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale */ in s3c2410_cpufreq_setrefresh()
48 refresh = (1 << 11) + 1 - refresh; in s3c2410_cpufreq_setrefresh()
50 s3c_freq_dbg("%s: refresh value %lu\n", __func__, refresh); in s3c2410_cpufreq_setrefresh()
54 refval |= refresh; in s3c2410_cpufreq_setrefresh()
Diotiming-s3c2412.c266 u32 refresh; in s3c2412_cpufreq_setrefresh() local
277 refresh = (cfg->freq.hclk / 100) * (board->refresh / 10); in s3c2412_cpufreq_setrefresh()
278 refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale */ in s3c2412_cpufreq_setrefresh()
279 refresh &= ((1 << 16) - 1); in s3c2412_cpufreq_setrefresh()
281 s3c_freq_dbg("%s: refresh value %u\n", __func__, (unsigned int)refresh); in s3c2412_cpufreq_setrefresh()
283 __raw_writel(refresh, S3C2412_REFRESH); in s3c2412_cpufreq_setrefresh()
/arch/cris/arch-v32/mach-fs/
Ddram_init.S64 ; Set timing parameters (refresh off to avoid Guinness TR 83)
96 ; Start refresh
107 .byte regk_bif_core_ref ; refresh
108 .byte regk_bif_core_ref ; refresh
109 .byte regk_bif_core_ref ; refresh
110 .byte regk_bif_core_ref ; refresh
111 .byte regk_bif_core_ref ; refresh
112 .byte regk_bif_core_ref ; refresh
113 .byte regk_bif_core_ref ; refresh
114 .byte regk_bif_core_ref ; refresh
/arch/cris/arch-v10/lib/
Ddram_init.S127 .byte 2 ; refresh
129 .byte 2 ; refresh
131 .byte 2 ; refresh
133 .byte 2 ; refresh
135 .byte 2 ; refresh
137 .byte 2 ; refresh
139 .byte 2 ; refresh
141 .byte 2 ; refresh
/arch/arm/mach-pxa/
Dsleep.S54 @ prepare SDRAM refresh settings
58 @ enable SDRAM self-refresh mode
95 @ prepare SDRAM refresh settings
99 @ enable SDRAM self-refresh mode
107 @ as possible to eliminate messing about with the refresh clock
159 @ external accesses after SDRAM is put in self-refresh mode
160 @ (see Errata 38 ...hangs when entering self-refresh mode)
165 @ put SDRAM into self-refresh
/arch/arm/mach-omap2/
Dsleep24xx.S73 orr r4, r4, #0x40 @ enable self refresh on idle req
84 bic r4, r4, #0x40 @ now clear self refresh bit.
88 nop @ start auto refresh only after clk ok
/arch/avr32/boards/atngw100/
Devklcd10x.c36 .refresh = 50,
74 .refresh = 50,
112 .refresh = 60,
Dmrmt.c63 .refresh = 59.94,
106 .refresh = 59.94,
/arch/arm/mach-prima2/
Dsleep.S41 @ refresh bit
47 @ the RAM is going to self refresh mode
/arch/arm/mach-imx/
Deukrea_mbimxsd35-baseboard.c47 .refresh = 60,
63 .refresh = 60,
80 .refresh = 60,
Deukrea_mbimxsd25-baseboard.c112 .refresh = 60,
128 .refresh = 60,
144 .refresh = 60,
Dmach-vpr200.c57 .refresh = 60,
73 .refresh = 60,
Dmach-pcm043.c47 .refresh = 60,
63 .refresh = 60,
/arch/arm/mach-nspire/
Dclcd.c21 .refresh = 60,
45 .refresh = 60,
/arch/sh/boards/mach-hp6xx/
Dpm_wakeup.S28 ! enable refresh
/arch/avr32/boards/merisc/
Ddisplay.c20 .refresh = 44,
/arch/arm/plat-samsung/include/plat/
Dcpu-freq.h120 unsigned int refresh; member
/arch/arm/mach-integrator/
Dimpd1.c79 .refresh = 60,
107 .refresh = 0,
135 .refresh = 0,
167 .refresh = 0,
/arch/frv/kernel/
Dsleep.S85 # when dram is in self-refresh state.
135 # put SDRAM in self-refresh mode
146 # put the SDRAM into self-refresh mode
152 # wait for SDRAM to reach self-refresh mode
189 # wake SDRAM from self-refresh mode
Dcmode.S118 # self-refresh mode. Execute the dummy load to all memory
154 # (14) Release the self-refresh of SDRAM.
/arch/avr32/boards/atstk1000/
Dsetup.c33 .refresh = 75,
/arch/arm/mach-s3c64xx/
Dmach-smartq5.c127 .refresh = 80,
Dmach-smartq7.c143 .refresh = 80,
/arch/arm/mach-omap1/
Dsleep.S81 @ prepare to put SDRAM into self-refresh manually
166 @ prepare to put SDRAM into self-refresh manually
236 @ Prepare to put SDRAM into self-refresh manually
/arch/unicore32/kernel/
Dsleep.S99 @ prepare DDR2 refresh settings
120 @ put DDR2 into self-refresh

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