Searched refs:refresh (Results 1 – 25 of 64) sorted by relevance
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/arch/arm/mach-s3c24xx/ |
D | cpufreq-utils.c | 36 unsigned long refresh; in s3c2410_cpufreq_setrefresh() local 46 refresh = (cfg->freq.hclk / 100) * (board->refresh / 10); in s3c2410_cpufreq_setrefresh() 47 refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale */ in s3c2410_cpufreq_setrefresh() 48 refresh = (1 << 11) + 1 - refresh; in s3c2410_cpufreq_setrefresh() 50 s3c_freq_dbg("%s: refresh value %lu\n", __func__, refresh); in s3c2410_cpufreq_setrefresh() 54 refval |= refresh; in s3c2410_cpufreq_setrefresh()
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D | iotiming-s3c2412.c | 266 u32 refresh; in s3c2412_cpufreq_setrefresh() local 277 refresh = (cfg->freq.hclk / 100) * (board->refresh / 10); in s3c2412_cpufreq_setrefresh() 278 refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale */ in s3c2412_cpufreq_setrefresh() 279 refresh &= ((1 << 16) - 1); in s3c2412_cpufreq_setrefresh() 281 s3c_freq_dbg("%s: refresh value %u\n", __func__, (unsigned int)refresh); in s3c2412_cpufreq_setrefresh() 283 __raw_writel(refresh, S3C2412_REFRESH); in s3c2412_cpufreq_setrefresh()
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/arch/cris/arch-v32/mach-fs/ |
D | dram_init.S | 64 ; Set timing parameters (refresh off to avoid Guinness TR 83) 96 ; Start refresh 107 .byte regk_bif_core_ref ; refresh 108 .byte regk_bif_core_ref ; refresh 109 .byte regk_bif_core_ref ; refresh 110 .byte regk_bif_core_ref ; refresh 111 .byte regk_bif_core_ref ; refresh 112 .byte regk_bif_core_ref ; refresh 113 .byte regk_bif_core_ref ; refresh 114 .byte regk_bif_core_ref ; refresh
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/arch/cris/arch-v10/lib/ |
D | dram_init.S | 127 .byte 2 ; refresh 129 .byte 2 ; refresh 131 .byte 2 ; refresh 133 .byte 2 ; refresh 135 .byte 2 ; refresh 137 .byte 2 ; refresh 139 .byte 2 ; refresh 141 .byte 2 ; refresh
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/arch/arm/mach-pxa/ |
D | sleep.S | 54 @ prepare SDRAM refresh settings 58 @ enable SDRAM self-refresh mode 95 @ prepare SDRAM refresh settings 99 @ enable SDRAM self-refresh mode 107 @ as possible to eliminate messing about with the refresh clock 159 @ external accesses after SDRAM is put in self-refresh mode 160 @ (see Errata 38 ...hangs when entering self-refresh mode) 165 @ put SDRAM into self-refresh
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/arch/arm/mach-omap2/ |
D | sleep24xx.S | 73 orr r4, r4, #0x40 @ enable self refresh on idle req 84 bic r4, r4, #0x40 @ now clear self refresh bit. 88 nop @ start auto refresh only after clk ok
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/arch/avr32/boards/atngw100/ |
D | evklcd10x.c | 36 .refresh = 50, 74 .refresh = 50, 112 .refresh = 60,
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D | mrmt.c | 63 .refresh = 59.94, 106 .refresh = 59.94,
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/arch/arm/mach-prima2/ |
D | sleep.S | 41 @ refresh bit 47 @ the RAM is going to self refresh mode
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/arch/arm/mach-imx/ |
D | eukrea_mbimxsd35-baseboard.c | 47 .refresh = 60, 63 .refresh = 60, 80 .refresh = 60,
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D | eukrea_mbimxsd25-baseboard.c | 112 .refresh = 60, 128 .refresh = 60, 144 .refresh = 60,
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D | mach-vpr200.c | 57 .refresh = 60, 73 .refresh = 60,
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D | mach-pcm043.c | 47 .refresh = 60, 63 .refresh = 60,
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/arch/arm/mach-nspire/ |
D | clcd.c | 21 .refresh = 60, 45 .refresh = 60,
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/arch/sh/boards/mach-hp6xx/ |
D | pm_wakeup.S | 28 ! enable refresh
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/arch/avr32/boards/merisc/ |
D | display.c | 20 .refresh = 44,
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/arch/arm/plat-samsung/include/plat/ |
D | cpu-freq.h | 120 unsigned int refresh; member
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/arch/arm/mach-integrator/ |
D | impd1.c | 79 .refresh = 60, 107 .refresh = 0, 135 .refresh = 0, 167 .refresh = 0,
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/arch/frv/kernel/ |
D | sleep.S | 85 # when dram is in self-refresh state. 135 # put SDRAM in self-refresh mode 146 # put the SDRAM into self-refresh mode 152 # wait for SDRAM to reach self-refresh mode 189 # wake SDRAM from self-refresh mode
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D | cmode.S | 118 # self-refresh mode. Execute the dummy load to all memory 154 # (14) Release the self-refresh of SDRAM.
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/arch/avr32/boards/atstk1000/ |
D | setup.c | 33 .refresh = 75,
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/arch/arm/mach-s3c64xx/ |
D | mach-smartq5.c | 127 .refresh = 80,
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D | mach-smartq7.c | 143 .refresh = 80,
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/arch/arm/mach-omap1/ |
D | sleep.S | 81 @ prepare to put SDRAM into self-refresh manually 166 @ prepare to put SDRAM into self-refresh manually 236 @ Prepare to put SDRAM into self-refresh manually
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/arch/unicore32/kernel/ |
D | sleep.S | 99 @ prepare DDR2 refresh settings 120 @ put DDR2 into self-refresh
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