1 /*
2 * the simple DMA Implementation for Blackfin
3 *
4 * Copyright 2007-2008 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9 #include <linux/module.h>
10
11 #include <asm/blackfin.h>
12 #include <asm/dma.h>
13
14 struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
15 (struct dma_register *) DMA1_0_NEXT_DESC_PTR,
16 (struct dma_register *) DMA1_1_NEXT_DESC_PTR,
17 (struct dma_register *) DMA1_2_NEXT_DESC_PTR,
18 (struct dma_register *) DMA1_3_NEXT_DESC_PTR,
19 (struct dma_register *) DMA1_4_NEXT_DESC_PTR,
20 (struct dma_register *) DMA1_5_NEXT_DESC_PTR,
21 (struct dma_register *) DMA1_6_NEXT_DESC_PTR,
22 (struct dma_register *) DMA1_7_NEXT_DESC_PTR,
23 (struct dma_register *) DMA1_8_NEXT_DESC_PTR,
24 (struct dma_register *) DMA1_9_NEXT_DESC_PTR,
25 (struct dma_register *) DMA1_10_NEXT_DESC_PTR,
26 (struct dma_register *) DMA1_11_NEXT_DESC_PTR,
27 (struct dma_register *) DMA2_0_NEXT_DESC_PTR,
28 (struct dma_register *) DMA2_1_NEXT_DESC_PTR,
29 (struct dma_register *) DMA2_2_NEXT_DESC_PTR,
30 (struct dma_register *) DMA2_3_NEXT_DESC_PTR,
31 (struct dma_register *) DMA2_4_NEXT_DESC_PTR,
32 (struct dma_register *) DMA2_5_NEXT_DESC_PTR,
33 (struct dma_register *) DMA2_6_NEXT_DESC_PTR,
34 (struct dma_register *) DMA2_7_NEXT_DESC_PTR,
35 (struct dma_register *) DMA2_8_NEXT_DESC_PTR,
36 (struct dma_register *) DMA2_9_NEXT_DESC_PTR,
37 (struct dma_register *) DMA2_10_NEXT_DESC_PTR,
38 (struct dma_register *) DMA2_11_NEXT_DESC_PTR,
39 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
40 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
41 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
42 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
43 (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
44 (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
45 (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
46 (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
47 (struct dma_register *) IMDMA_D0_NEXT_DESC_PTR,
48 (struct dma_register *) IMDMA_S0_NEXT_DESC_PTR,
49 (struct dma_register *) IMDMA_D1_NEXT_DESC_PTR,
50 (struct dma_register *) IMDMA_S1_NEXT_DESC_PTR,
51 };
52 EXPORT_SYMBOL(dma_io_base_addr);
53
channel2irq(unsigned int channel)54 int channel2irq(unsigned int channel)
55 {
56 int ret_irq = -1;
57
58 switch (channel) {
59 case CH_PPI0:
60 ret_irq = IRQ_PPI0;
61 break;
62 case CH_PPI1:
63 ret_irq = IRQ_PPI1;
64 break;
65 case CH_SPORT0_RX:
66 ret_irq = IRQ_SPORT0_RX;
67 break;
68 case CH_SPORT0_TX:
69 ret_irq = IRQ_SPORT0_TX;
70 break;
71 case CH_SPORT1_RX:
72 ret_irq = IRQ_SPORT1_RX;
73 break;
74 case CH_SPORT1_TX:
75 ret_irq = IRQ_SPORT1_TX;
76 break;
77 case CH_SPI:
78 ret_irq = IRQ_SPI;
79 break;
80 case CH_UART_RX:
81 ret_irq = IRQ_UART_RX;
82 break;
83 case CH_UART_TX:
84 ret_irq = IRQ_UART_TX;
85 break;
86
87 case CH_MEM_STREAM0_SRC:
88 case CH_MEM_STREAM0_DEST:
89 ret_irq = IRQ_MEM_DMA0;
90 break;
91 case CH_MEM_STREAM1_SRC:
92 case CH_MEM_STREAM1_DEST:
93 ret_irq = IRQ_MEM_DMA1;
94 break;
95 case CH_MEM_STREAM2_SRC:
96 case CH_MEM_STREAM2_DEST:
97 ret_irq = IRQ_MEM_DMA2;
98 break;
99 case CH_MEM_STREAM3_SRC:
100 case CH_MEM_STREAM3_DEST:
101 ret_irq = IRQ_MEM_DMA3;
102 break;
103
104 case CH_IMEM_STREAM0_SRC:
105 case CH_IMEM_STREAM0_DEST:
106 ret_irq = IRQ_IMEM_DMA0;
107 break;
108 case CH_IMEM_STREAM1_SRC:
109 case CH_IMEM_STREAM1_DEST:
110 ret_irq = IRQ_IMEM_DMA1;
111 break;
112 }
113 return ret_irq;
114 }
115