1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include <engine/software.h>
26 #include <engine/disp.h>
27
28 #include <nvif/class.h>
29
30 #include "nv50.h"
31
32 /*******************************************************************************
33 * EVO master channel object
34 ******************************************************************************/
35
36 const struct nv50_disp_mthd_list
37 nv94_disp_mast_mthd_sor = {
38 .mthd = 0x0040,
39 .addr = 0x000008,
40 .data = {
41 { 0x0600, 0x610794 },
42 {}
43 }
44 };
45
46 const struct nv50_disp_mthd_chan
47 nv94_disp_mast_mthd_chan = {
48 .name = "Core",
49 .addr = 0x000000,
50 .data = {
51 { "Global", 1, &nv50_disp_mast_mthd_base },
52 { "DAC", 3, &nv84_disp_mast_mthd_dac },
53 { "SOR", 4, &nv94_disp_mast_mthd_sor },
54 { "PIOR", 3, &nv50_disp_mast_mthd_pior },
55 { "HEAD", 2, &nv84_disp_mast_mthd_head },
56 {}
57 }
58 };
59
60 /*******************************************************************************
61 * Base display object
62 ******************************************************************************/
63
64 static struct nouveau_oclass
65 nv94_disp_sclass[] = {
66 { GT206_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base },
67 { GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base },
68 { GT200_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
69 { G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
70 { G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
71 {}
72 };
73
74 static struct nouveau_oclass
75 nv94_disp_base_oclass[] = {
76 { GT206_DISP, &nv50_disp_base_ofuncs },
77 {}
78 };
79
80 /*******************************************************************************
81 * Display engine implementation
82 ******************************************************************************/
83
84 static int
nv94_disp_ctor(struct nouveau_object * parent,struct nouveau_object * engine,struct nouveau_oclass * oclass,void * data,u32 size,struct nouveau_object ** pobject)85 nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
86 struct nouveau_oclass *oclass, void *data, u32 size,
87 struct nouveau_object **pobject)
88 {
89 struct nv50_disp_priv *priv;
90 int ret;
91
92 ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
93 "display", &priv);
94 *pobject = nv_object(priv);
95 if (ret)
96 return ret;
97
98 ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
99 if (ret)
100 return ret;
101
102 nv_engine(priv)->sclass = nv94_disp_base_oclass;
103 nv_engine(priv)->cclass = &nv50_disp_cclass;
104 nv_subdev(priv)->intr = nv50_disp_intr;
105 INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
106 priv->sclass = nv94_disp_sclass;
107 priv->head.nr = 2;
108 priv->dac.nr = 3;
109 priv->sor.nr = 4;
110 priv->pior.nr = 3;
111 priv->dac.power = nv50_dac_power;
112 priv->dac.sense = nv50_dac_sense;
113 priv->sor.power = nv50_sor_power;
114 priv->sor.hdmi = nv84_hdmi_ctrl;
115 priv->pior.power = nv50_pior_power;
116 return 0;
117 }
118
119 struct nouveau_oclass *
120 nv94_disp_outp_sclass[] = {
121 &nv50_pior_dp_impl.base.base,
122 &nv94_sor_dp_impl.base.base,
123 NULL
124 };
125
126 struct nouveau_oclass *
127 nv94_disp_oclass = &(struct nv50_disp_impl) {
128 .base.base.handle = NV_ENGINE(DISP, 0x88),
129 .base.base.ofuncs = &(struct nouveau_ofuncs) {
130 .ctor = nv94_disp_ctor,
131 .dtor = _nouveau_disp_dtor,
132 .init = _nouveau_disp_init,
133 .fini = _nouveau_disp_fini,
134 },
135 .base.vblank = &nv50_disp_vblank_func,
136 .base.outp = nv94_disp_outp_sclass,
137 .mthd.core = &nv94_disp_mast_mthd_chan,
138 .mthd.base = &nv84_disp_sync_mthd_chan,
139 .mthd.ovly = &nv84_disp_ovly_mthd_chan,
140 .mthd.prev = 0x000004,
141 .head.scanoutpos = nv50_disp_base_scanoutpos,
142 }.base.base;
143