1 /*
2 * Freescale Vybrid vf610 ADC driver
3 *
4 * Copyright 2013 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/interrupt.h>
24 #include <linux/delay.h>
25 #include <linux/kernel.h>
26 #include <linux/slab.h>
27 #include <linux/io.h>
28 #include <linux/clk.h>
29 #include <linux/completion.h>
30 #include <linux/of.h>
31 #include <linux/of_irq.h>
32 #include <linux/regulator/consumer.h>
33 #include <linux/of_platform.h>
34 #include <linux/err.h>
35
36 #include <linux/iio/iio.h>
37 #include <linux/iio/sysfs.h>
38 #include <linux/iio/driver.h>
39
40 /* This will be the driver name the kernel reports */
41 #define DRIVER_NAME "vf610-adc"
42
43 /* Vybrid/IMX ADC registers */
44 #define VF610_REG_ADC_HC0 0x00
45 #define VF610_REG_ADC_HC1 0x04
46 #define VF610_REG_ADC_HS 0x08
47 #define VF610_REG_ADC_R0 0x0c
48 #define VF610_REG_ADC_R1 0x10
49 #define VF610_REG_ADC_CFG 0x14
50 #define VF610_REG_ADC_GC 0x18
51 #define VF610_REG_ADC_GS 0x1c
52 #define VF610_REG_ADC_CV 0x20
53 #define VF610_REG_ADC_OFS 0x24
54 #define VF610_REG_ADC_CAL 0x28
55 #define VF610_REG_ADC_PCTL 0x30
56
57 /* Configuration register field define */
58 #define VF610_ADC_MODE_BIT8 0x00
59 #define VF610_ADC_MODE_BIT10 0x04
60 #define VF610_ADC_MODE_BIT12 0x08
61 #define VF610_ADC_MODE_MASK 0x0c
62 #define VF610_ADC_BUSCLK2_SEL 0x01
63 #define VF610_ADC_ALTCLK_SEL 0x02
64 #define VF610_ADC_ADACK_SEL 0x03
65 #define VF610_ADC_ADCCLK_MASK 0x03
66 #define VF610_ADC_CLK_DIV2 0x20
67 #define VF610_ADC_CLK_DIV4 0x40
68 #define VF610_ADC_CLK_DIV8 0x60
69 #define VF610_ADC_CLK_MASK 0x60
70 #define VF610_ADC_ADLSMP_LONG 0x10
71 #define VF610_ADC_ADSTS_MASK 0x300
72 #define VF610_ADC_ADLPC_EN 0x80
73 #define VF610_ADC_ADHSC_EN 0x400
74 #define VF610_ADC_REFSEL_VALT 0x800
75 #define VF610_ADC_REFSEL_VBG 0x1000
76 #define VF610_ADC_ADTRG_HARD 0x2000
77 #define VF610_ADC_AVGS_8 0x4000
78 #define VF610_ADC_AVGS_16 0x8000
79 #define VF610_ADC_AVGS_32 0xC000
80 #define VF610_ADC_AVGS_MASK 0xC000
81 #define VF610_ADC_OVWREN 0x10000
82
83 /* General control register field define */
84 #define VF610_ADC_ADACKEN 0x1
85 #define VF610_ADC_DMAEN 0x2
86 #define VF610_ADC_ACREN 0x4
87 #define VF610_ADC_ACFGT 0x8
88 #define VF610_ADC_ACFE 0x10
89 #define VF610_ADC_AVGEN 0x20
90 #define VF610_ADC_ADCON 0x40
91 #define VF610_ADC_CAL 0x80
92
93 /* Other field define */
94 #define VF610_ADC_ADCHC(x) ((x) & 0xF)
95 #define VF610_ADC_AIEN (0x1 << 7)
96 #define VF610_ADC_CONV_DISABLE 0x1F
97 #define VF610_ADC_HS_COCO0 0x1
98 #define VF610_ADC_CALF 0x2
99 #define VF610_ADC_TIMEOUT msecs_to_jiffies(100)
100
101 enum clk_sel {
102 VF610_ADCIOC_BUSCLK_SET,
103 VF610_ADCIOC_ALTCLK_SET,
104 VF610_ADCIOC_ADACK_SET,
105 };
106
107 enum vol_ref {
108 VF610_ADCIOC_VR_VREF_SET,
109 VF610_ADCIOC_VR_VALT_SET,
110 VF610_ADCIOC_VR_VBG_SET,
111 };
112
113 enum average_sel {
114 VF610_ADC_SAMPLE_1,
115 VF610_ADC_SAMPLE_4,
116 VF610_ADC_SAMPLE_8,
117 VF610_ADC_SAMPLE_16,
118 VF610_ADC_SAMPLE_32,
119 };
120
121 struct vf610_adc_feature {
122 enum clk_sel clk_sel;
123 enum vol_ref vol_ref;
124
125 int clk_div;
126 int sample_rate;
127 int res_mode;
128
129 bool lpm;
130 bool calibration;
131 bool ovwren;
132 };
133
134 struct vf610_adc {
135 struct device *dev;
136 void __iomem *regs;
137 struct clk *clk;
138
139 u32 vref_uv;
140 u32 value;
141 struct regulator *vref;
142 struct vf610_adc_feature adc_feature;
143
144 u32 sample_freq_avail[5];
145
146 struct completion completion;
147 };
148
149 static const u32 vf610_hw_avgs[] = { 1, 4, 8, 16, 32 };
150
151 #define VF610_ADC_CHAN(_idx, _chan_type) { \
152 .type = (_chan_type), \
153 .indexed = 1, \
154 .channel = (_idx), \
155 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
156 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
157 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
158 }
159
160 static const struct iio_chan_spec vf610_adc_iio_channels[] = {
161 VF610_ADC_CHAN(0, IIO_VOLTAGE),
162 VF610_ADC_CHAN(1, IIO_VOLTAGE),
163 VF610_ADC_CHAN(2, IIO_VOLTAGE),
164 VF610_ADC_CHAN(3, IIO_VOLTAGE),
165 VF610_ADC_CHAN(4, IIO_VOLTAGE),
166 VF610_ADC_CHAN(5, IIO_VOLTAGE),
167 VF610_ADC_CHAN(6, IIO_VOLTAGE),
168 VF610_ADC_CHAN(7, IIO_VOLTAGE),
169 VF610_ADC_CHAN(8, IIO_VOLTAGE),
170 VF610_ADC_CHAN(9, IIO_VOLTAGE),
171 VF610_ADC_CHAN(10, IIO_VOLTAGE),
172 VF610_ADC_CHAN(11, IIO_VOLTAGE),
173 VF610_ADC_CHAN(12, IIO_VOLTAGE),
174 VF610_ADC_CHAN(13, IIO_VOLTAGE),
175 VF610_ADC_CHAN(14, IIO_VOLTAGE),
176 VF610_ADC_CHAN(15, IIO_VOLTAGE),
177 /* sentinel */
178 };
179
vf610_adc_calculate_rates(struct vf610_adc * info)180 static inline void vf610_adc_calculate_rates(struct vf610_adc *info)
181 {
182 unsigned long adck_rate, ipg_rate = clk_get_rate(info->clk);
183 int i;
184
185 /*
186 * Calculate ADC sample frequencies
187 * Sample time unit is ADCK cycles. ADCK clk source is ipg clock,
188 * which is the same as bus clock.
189 *
190 * ADC conversion time = SFCAdder + AverageNum x (BCT + LSTAdder)
191 * SFCAdder: fixed to 6 ADCK cycles
192 * AverageNum: 1, 4, 8, 16, 32 samples for hardware average.
193 * BCT (Base Conversion Time): fixed to 25 ADCK cycles for 12 bit mode
194 * LSTAdder(Long Sample Time): fixed to 3 ADCK cycles
195 */
196 adck_rate = ipg_rate / info->adc_feature.clk_div;
197 for (i = 0; i < ARRAY_SIZE(vf610_hw_avgs); i++)
198 info->sample_freq_avail[i] =
199 adck_rate / (6 + vf610_hw_avgs[i] * (25 + 3));
200 }
201
vf610_adc_cfg_init(struct vf610_adc * info)202 static inline void vf610_adc_cfg_init(struct vf610_adc *info)
203 {
204 struct vf610_adc_feature *adc_feature = &info->adc_feature;
205
206 /* set default Configuration for ADC controller */
207 adc_feature->clk_sel = VF610_ADCIOC_BUSCLK_SET;
208 adc_feature->vol_ref = VF610_ADCIOC_VR_VREF_SET;
209
210 adc_feature->calibration = true;
211 adc_feature->ovwren = true;
212
213 adc_feature->res_mode = 12;
214 adc_feature->sample_rate = 1;
215 adc_feature->lpm = true;
216
217 /* Use a save ADCK which is below 20MHz on all devices */
218 adc_feature->clk_div = 8;
219
220 vf610_adc_calculate_rates(info);
221 }
222
vf610_adc_cfg_post_set(struct vf610_adc * info)223 static void vf610_adc_cfg_post_set(struct vf610_adc *info)
224 {
225 struct vf610_adc_feature *adc_feature = &info->adc_feature;
226 int cfg_data = 0;
227 int gc_data = 0;
228
229 switch (adc_feature->clk_sel) {
230 case VF610_ADCIOC_ALTCLK_SET:
231 cfg_data |= VF610_ADC_ALTCLK_SEL;
232 break;
233 case VF610_ADCIOC_ADACK_SET:
234 cfg_data |= VF610_ADC_ADACK_SEL;
235 break;
236 default:
237 break;
238 }
239
240 /* low power set for calibration */
241 cfg_data |= VF610_ADC_ADLPC_EN;
242
243 /* enable high speed for calibration */
244 cfg_data |= VF610_ADC_ADHSC_EN;
245
246 /* voltage reference */
247 switch (adc_feature->vol_ref) {
248 case VF610_ADCIOC_VR_VREF_SET:
249 break;
250 case VF610_ADCIOC_VR_VALT_SET:
251 cfg_data |= VF610_ADC_REFSEL_VALT;
252 break;
253 case VF610_ADCIOC_VR_VBG_SET:
254 cfg_data |= VF610_ADC_REFSEL_VBG;
255 break;
256 default:
257 dev_err(info->dev, "error voltage reference\n");
258 }
259
260 /* data overwrite enable */
261 if (adc_feature->ovwren)
262 cfg_data |= VF610_ADC_OVWREN;
263
264 writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
265 writel(gc_data, info->regs + VF610_REG_ADC_GC);
266 }
267
vf610_adc_calibration(struct vf610_adc * info)268 static void vf610_adc_calibration(struct vf610_adc *info)
269 {
270 int adc_gc, hc_cfg;
271 int timeout;
272
273 if (!info->adc_feature.calibration)
274 return;
275
276 /* enable calibration interrupt */
277 hc_cfg = VF610_ADC_AIEN | VF610_ADC_CONV_DISABLE;
278 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
279
280 adc_gc = readl(info->regs + VF610_REG_ADC_GC);
281 writel(adc_gc | VF610_ADC_CAL, info->regs + VF610_REG_ADC_GC);
282
283 timeout = wait_for_completion_timeout
284 (&info->completion, VF610_ADC_TIMEOUT);
285 if (timeout == 0)
286 dev_err(info->dev, "Timeout for adc calibration\n");
287
288 adc_gc = readl(info->regs + VF610_REG_ADC_GS);
289 if (adc_gc & VF610_ADC_CALF)
290 dev_err(info->dev, "ADC calibration failed\n");
291
292 info->adc_feature.calibration = false;
293 }
294
vf610_adc_cfg_set(struct vf610_adc * info)295 static void vf610_adc_cfg_set(struct vf610_adc *info)
296 {
297 struct vf610_adc_feature *adc_feature = &(info->adc_feature);
298 int cfg_data;
299
300 cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
301
302 cfg_data &= ~VF610_ADC_ADLPC_EN;
303 if (adc_feature->lpm)
304 cfg_data |= VF610_ADC_ADLPC_EN;
305
306 cfg_data &= ~VF610_ADC_ADHSC_EN;
307
308 writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
309 }
310
vf610_adc_sample_set(struct vf610_adc * info)311 static void vf610_adc_sample_set(struct vf610_adc *info)
312 {
313 struct vf610_adc_feature *adc_feature = &(info->adc_feature);
314 int cfg_data, gc_data;
315
316 cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
317 gc_data = readl(info->regs + VF610_REG_ADC_GC);
318
319 /* resolution mode */
320 cfg_data &= ~VF610_ADC_MODE_MASK;
321 switch (adc_feature->res_mode) {
322 case 8:
323 cfg_data |= VF610_ADC_MODE_BIT8;
324 break;
325 case 10:
326 cfg_data |= VF610_ADC_MODE_BIT10;
327 break;
328 case 12:
329 cfg_data |= VF610_ADC_MODE_BIT12;
330 break;
331 default:
332 dev_err(info->dev, "error resolution mode\n");
333 break;
334 }
335
336 /* clock select and clock divider */
337 cfg_data &= ~(VF610_ADC_CLK_MASK | VF610_ADC_ADCCLK_MASK);
338 switch (adc_feature->clk_div) {
339 case 1:
340 break;
341 case 2:
342 cfg_data |= VF610_ADC_CLK_DIV2;
343 break;
344 case 4:
345 cfg_data |= VF610_ADC_CLK_DIV4;
346 break;
347 case 8:
348 cfg_data |= VF610_ADC_CLK_DIV8;
349 break;
350 case 16:
351 switch (adc_feature->clk_sel) {
352 case VF610_ADCIOC_BUSCLK_SET:
353 cfg_data |= VF610_ADC_BUSCLK2_SEL | VF610_ADC_CLK_DIV8;
354 break;
355 default:
356 dev_err(info->dev, "error clk divider\n");
357 break;
358 }
359 break;
360 }
361
362 /* Use the short sample mode */
363 cfg_data &= ~(VF610_ADC_ADLSMP_LONG | VF610_ADC_ADSTS_MASK);
364
365 /* update hardware average selection */
366 cfg_data &= ~VF610_ADC_AVGS_MASK;
367 gc_data &= ~VF610_ADC_AVGEN;
368 switch (adc_feature->sample_rate) {
369 case VF610_ADC_SAMPLE_1:
370 break;
371 case VF610_ADC_SAMPLE_4:
372 gc_data |= VF610_ADC_AVGEN;
373 break;
374 case VF610_ADC_SAMPLE_8:
375 gc_data |= VF610_ADC_AVGEN;
376 cfg_data |= VF610_ADC_AVGS_8;
377 break;
378 case VF610_ADC_SAMPLE_16:
379 gc_data |= VF610_ADC_AVGEN;
380 cfg_data |= VF610_ADC_AVGS_16;
381 break;
382 case VF610_ADC_SAMPLE_32:
383 gc_data |= VF610_ADC_AVGEN;
384 cfg_data |= VF610_ADC_AVGS_32;
385 break;
386 default:
387 dev_err(info->dev,
388 "error hardware sample average select\n");
389 }
390
391 writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
392 writel(gc_data, info->regs + VF610_REG_ADC_GC);
393 }
394
vf610_adc_hw_init(struct vf610_adc * info)395 static void vf610_adc_hw_init(struct vf610_adc *info)
396 {
397 /* CFG: Feature set */
398 vf610_adc_cfg_post_set(info);
399 vf610_adc_sample_set(info);
400
401 /* adc calibration */
402 vf610_adc_calibration(info);
403
404 /* CFG: power and speed set */
405 vf610_adc_cfg_set(info);
406 }
407
vf610_adc_read_data(struct vf610_adc * info)408 static int vf610_adc_read_data(struct vf610_adc *info)
409 {
410 int result;
411
412 result = readl(info->regs + VF610_REG_ADC_R0);
413
414 switch (info->adc_feature.res_mode) {
415 case 8:
416 result &= 0xFF;
417 break;
418 case 10:
419 result &= 0x3FF;
420 break;
421 case 12:
422 result &= 0xFFF;
423 break;
424 default:
425 break;
426 }
427
428 return result;
429 }
430
vf610_adc_isr(int irq,void * dev_id)431 static irqreturn_t vf610_adc_isr(int irq, void *dev_id)
432 {
433 struct vf610_adc *info = (struct vf610_adc *)dev_id;
434 int coco;
435
436 coco = readl(info->regs + VF610_REG_ADC_HS);
437 if (coco & VF610_ADC_HS_COCO0) {
438 info->value = vf610_adc_read_data(info);
439 complete(&info->completion);
440 }
441
442 return IRQ_HANDLED;
443 }
444
vf610_show_samp_freq_avail(struct device * dev,struct device_attribute * attr,char * buf)445 static ssize_t vf610_show_samp_freq_avail(struct device *dev,
446 struct device_attribute *attr, char *buf)
447 {
448 struct vf610_adc *info = iio_priv(dev_to_iio_dev(dev));
449 size_t len = 0;
450 int i;
451
452 for (i = 0; i < ARRAY_SIZE(info->sample_freq_avail); i++)
453 len += scnprintf(buf + len, PAGE_SIZE - len,
454 "%u ", info->sample_freq_avail[i]);
455
456 /* replace trailing space by newline */
457 buf[len - 1] = '\n';
458
459 return len;
460 }
461
462 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(vf610_show_samp_freq_avail);
463
464 static struct attribute *vf610_attributes[] = {
465 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
466 NULL
467 };
468
469 static const struct attribute_group vf610_attribute_group = {
470 .attrs = vf610_attributes,
471 };
472
vf610_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)473 static int vf610_read_raw(struct iio_dev *indio_dev,
474 struct iio_chan_spec const *chan,
475 int *val,
476 int *val2,
477 long mask)
478 {
479 struct vf610_adc *info = iio_priv(indio_dev);
480 unsigned int hc_cfg;
481 long ret;
482
483 switch (mask) {
484 case IIO_CHAN_INFO_RAW:
485 mutex_lock(&indio_dev->mlock);
486 reinit_completion(&info->completion);
487
488 hc_cfg = VF610_ADC_ADCHC(chan->channel);
489 hc_cfg |= VF610_ADC_AIEN;
490 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
491 ret = wait_for_completion_interruptible_timeout
492 (&info->completion, VF610_ADC_TIMEOUT);
493 if (ret == 0) {
494 mutex_unlock(&indio_dev->mlock);
495 return -ETIMEDOUT;
496 }
497 if (ret < 0) {
498 mutex_unlock(&indio_dev->mlock);
499 return ret;
500 }
501
502 *val = info->value;
503 mutex_unlock(&indio_dev->mlock);
504 return IIO_VAL_INT;
505
506 case IIO_CHAN_INFO_SCALE:
507 *val = info->vref_uv / 1000;
508 *val2 = info->adc_feature.res_mode;
509 return IIO_VAL_FRACTIONAL_LOG2;
510
511 case IIO_CHAN_INFO_SAMP_FREQ:
512 *val = info->sample_freq_avail[info->adc_feature.sample_rate];
513 *val2 = 0;
514 return IIO_VAL_INT;
515
516 default:
517 break;
518 }
519
520 return -EINVAL;
521 }
522
vf610_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)523 static int vf610_write_raw(struct iio_dev *indio_dev,
524 struct iio_chan_spec const *chan,
525 int val,
526 int val2,
527 long mask)
528 {
529 struct vf610_adc *info = iio_priv(indio_dev);
530 int i;
531
532 switch (mask) {
533 case IIO_CHAN_INFO_SAMP_FREQ:
534 for (i = 0;
535 i < ARRAY_SIZE(info->sample_freq_avail);
536 i++)
537 if (val == info->sample_freq_avail[i]) {
538 info->adc_feature.sample_rate = i;
539 vf610_adc_sample_set(info);
540 return 0;
541 }
542 break;
543
544 default:
545 break;
546 }
547
548 return -EINVAL;
549 }
550
vf610_adc_reg_access(struct iio_dev * indio_dev,unsigned reg,unsigned writeval,unsigned * readval)551 static int vf610_adc_reg_access(struct iio_dev *indio_dev,
552 unsigned reg, unsigned writeval,
553 unsigned *readval)
554 {
555 struct vf610_adc *info = iio_priv(indio_dev);
556
557 if ((readval == NULL) ||
558 (!(reg % 4) || (reg > VF610_REG_ADC_PCTL)))
559 return -EINVAL;
560
561 *readval = readl(info->regs + reg);
562
563 return 0;
564 }
565
566 static const struct iio_info vf610_adc_iio_info = {
567 .driver_module = THIS_MODULE,
568 .read_raw = &vf610_read_raw,
569 .write_raw = &vf610_write_raw,
570 .debugfs_reg_access = &vf610_adc_reg_access,
571 .attrs = &vf610_attribute_group,
572 };
573
574 static const struct of_device_id vf610_adc_match[] = {
575 { .compatible = "fsl,vf610-adc", },
576 { /* sentinel */ }
577 };
578 MODULE_DEVICE_TABLE(of, vf610_adc_match);
579
vf610_adc_probe(struct platform_device * pdev)580 static int vf610_adc_probe(struct platform_device *pdev)
581 {
582 struct vf610_adc *info;
583 struct iio_dev *indio_dev;
584 struct resource *mem;
585 int irq;
586 int ret;
587
588 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct vf610_adc));
589 if (!indio_dev) {
590 dev_err(&pdev->dev, "Failed allocating iio device\n");
591 return -ENOMEM;
592 }
593
594 info = iio_priv(indio_dev);
595 info->dev = &pdev->dev;
596
597 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
598 info->regs = devm_ioremap_resource(&pdev->dev, mem);
599 if (IS_ERR(info->regs))
600 return PTR_ERR(info->regs);
601
602 irq = platform_get_irq(pdev, 0);
603 if (irq <= 0) {
604 dev_err(&pdev->dev, "no irq resource?\n");
605 return -EINVAL;
606 }
607
608 ret = devm_request_irq(info->dev, irq,
609 vf610_adc_isr, 0,
610 dev_name(&pdev->dev), info);
611 if (ret < 0) {
612 dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", irq);
613 return ret;
614 }
615
616 info->clk = devm_clk_get(&pdev->dev, "adc");
617 if (IS_ERR(info->clk)) {
618 dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
619 PTR_ERR(info->clk));
620 ret = PTR_ERR(info->clk);
621 return ret;
622 }
623
624 info->vref = devm_regulator_get(&pdev->dev, "vref");
625 if (IS_ERR(info->vref))
626 return PTR_ERR(info->vref);
627
628 ret = regulator_enable(info->vref);
629 if (ret)
630 return ret;
631
632 info->vref_uv = regulator_get_voltage(info->vref);
633
634 platform_set_drvdata(pdev, indio_dev);
635
636 init_completion(&info->completion);
637
638 indio_dev->name = dev_name(&pdev->dev);
639 indio_dev->dev.parent = &pdev->dev;
640 indio_dev->dev.of_node = pdev->dev.of_node;
641 indio_dev->info = &vf610_adc_iio_info;
642 indio_dev->modes = INDIO_DIRECT_MODE;
643 indio_dev->channels = vf610_adc_iio_channels;
644 indio_dev->num_channels = ARRAY_SIZE(vf610_adc_iio_channels);
645
646 ret = clk_prepare_enable(info->clk);
647 if (ret) {
648 dev_err(&pdev->dev,
649 "Could not prepare or enable the clock.\n");
650 goto error_adc_clk_enable;
651 }
652
653 vf610_adc_cfg_init(info);
654 vf610_adc_hw_init(info);
655
656 ret = iio_device_register(indio_dev);
657 if (ret) {
658 dev_err(&pdev->dev, "Couldn't register the device.\n");
659 goto error_iio_device_register;
660 }
661
662 return 0;
663
664
665 error_iio_device_register:
666 clk_disable_unprepare(info->clk);
667 error_adc_clk_enable:
668 regulator_disable(info->vref);
669
670 return ret;
671 }
672
vf610_adc_remove(struct platform_device * pdev)673 static int vf610_adc_remove(struct platform_device *pdev)
674 {
675 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
676 struct vf610_adc *info = iio_priv(indio_dev);
677
678 iio_device_unregister(indio_dev);
679 regulator_disable(info->vref);
680 clk_disable_unprepare(info->clk);
681
682 return 0;
683 }
684
685 #ifdef CONFIG_PM_SLEEP
vf610_adc_suspend(struct device * dev)686 static int vf610_adc_suspend(struct device *dev)
687 {
688 struct iio_dev *indio_dev = dev_get_drvdata(dev);
689 struct vf610_adc *info = iio_priv(indio_dev);
690 int hc_cfg;
691
692 /* ADC controller enters to stop mode */
693 hc_cfg = readl(info->regs + VF610_REG_ADC_HC0);
694 hc_cfg |= VF610_ADC_CONV_DISABLE;
695 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
696
697 clk_disable_unprepare(info->clk);
698 regulator_disable(info->vref);
699
700 return 0;
701 }
702
vf610_adc_resume(struct device * dev)703 static int vf610_adc_resume(struct device *dev)
704 {
705 struct iio_dev *indio_dev = dev_get_drvdata(dev);
706 struct vf610_adc *info = iio_priv(indio_dev);
707 int ret;
708
709 ret = regulator_enable(info->vref);
710 if (ret)
711 return ret;
712
713 ret = clk_prepare_enable(info->clk);
714 if (ret)
715 return ret;
716
717 vf610_adc_hw_init(info);
718
719 return 0;
720 }
721 #endif
722
723 static SIMPLE_DEV_PM_OPS(vf610_adc_pm_ops,
724 vf610_adc_suspend,
725 vf610_adc_resume);
726
727 static struct platform_driver vf610_adc_driver = {
728 .probe = vf610_adc_probe,
729 .remove = vf610_adc_remove,
730 .driver = {
731 .name = DRIVER_NAME,
732 .of_match_table = vf610_adc_match,
733 .pm = &vf610_adc_pm_ops,
734 },
735 };
736
737 module_platform_driver(vf610_adc_driver);
738
739 MODULE_AUTHOR("Fugang Duan <B38611@freescale.com>");
740 MODULE_DESCRIPTION("Freescale VF610 ADC driver");
741 MODULE_LICENSE("GPL v2");
742