1 /*
2 * Marvell Armada 370 and Armada XP SoC IRQ handling
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/irq.h>
20 #include <linux/interrupt.h>
21 #include <linux/irqchip/chained_irq.h>
22 #include <linux/cpu.h>
23 #include <linux/io.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_pci.h>
27 #include <linux/irqdomain.h>
28 #include <linux/slab.h>
29 #include <linux/msi.h>
30 #include <asm/mach/arch.h>
31 #include <asm/exception.h>
32 #include <asm/smp_plat.h>
33 #include <asm/mach/irq.h>
34
35 #include "irqchip.h"
36
37 /* Interrupt Controller Registers Map */
38 #define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
39 #define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
40
41 #define ARMADA_370_XP_INT_CONTROL (0x00)
42 #define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
43 #define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
44 #define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4)
45 #define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF
46 #define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << cpuid)
47
48 #define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
49 #define ARMADA_375_PPI_CAUSE (0x10)
50
51 #define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4)
52 #define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc)
53 #define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8)
54
55 #define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
56
57 #define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5)
58
59 #define IPI_DOORBELL_START (0)
60 #define IPI_DOORBELL_END (8)
61 #define IPI_DOORBELL_MASK 0xFF
62 #define PCI_MSI_DOORBELL_START (16)
63 #define PCI_MSI_DOORBELL_NR (16)
64 #define PCI_MSI_DOORBELL_END (32)
65 #define PCI_MSI_DOORBELL_MASK 0xFFFF0000
66
67 static void __iomem *per_cpu_int_base;
68 static void __iomem *main_int_base;
69 static struct irq_domain *armada_370_xp_mpic_domain;
70 static int parent_irq;
71 #ifdef CONFIG_PCI_MSI
72 static struct irq_domain *armada_370_xp_msi_domain;
73 static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
74 static DEFINE_MUTEX(msi_used_lock);
75 static phys_addr_t msi_doorbell_addr;
76 #endif
77
78 /*
79 * In SMP mode:
80 * For shared global interrupts, mask/unmask global enable bit
81 * For CPU interrupts, mask/unmask the calling CPU's bit
82 */
armada_370_xp_irq_mask(struct irq_data * d)83 static void armada_370_xp_irq_mask(struct irq_data *d)
84 {
85 irq_hw_number_t hwirq = irqd_to_hwirq(d);
86
87 if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
88 writel(hwirq, main_int_base +
89 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
90 else
91 writel(hwirq, per_cpu_int_base +
92 ARMADA_370_XP_INT_SET_MASK_OFFS);
93 }
94
armada_370_xp_irq_unmask(struct irq_data * d)95 static void armada_370_xp_irq_unmask(struct irq_data *d)
96 {
97 irq_hw_number_t hwirq = irqd_to_hwirq(d);
98
99 if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
100 writel(hwirq, main_int_base +
101 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
102 else
103 writel(hwirq, per_cpu_int_base +
104 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
105 }
106
107 #ifdef CONFIG_PCI_MSI
108
armada_370_xp_alloc_msi(void)109 static int armada_370_xp_alloc_msi(void)
110 {
111 int hwirq;
112
113 mutex_lock(&msi_used_lock);
114 hwirq = find_first_zero_bit(&msi_used, PCI_MSI_DOORBELL_NR);
115 if (hwirq >= PCI_MSI_DOORBELL_NR)
116 hwirq = -ENOSPC;
117 else
118 set_bit(hwirq, msi_used);
119 mutex_unlock(&msi_used_lock);
120
121 return hwirq;
122 }
123
armada_370_xp_free_msi(int hwirq)124 static void armada_370_xp_free_msi(int hwirq)
125 {
126 mutex_lock(&msi_used_lock);
127 if (!test_bit(hwirq, msi_used))
128 pr_err("trying to free unused MSI#%d\n", hwirq);
129 else
130 clear_bit(hwirq, msi_used);
131 mutex_unlock(&msi_used_lock);
132 }
133
armada_370_xp_setup_msi_irq(struct msi_chip * chip,struct pci_dev * pdev,struct msi_desc * desc)134 static int armada_370_xp_setup_msi_irq(struct msi_chip *chip,
135 struct pci_dev *pdev,
136 struct msi_desc *desc)
137 {
138 struct msi_msg msg;
139 int virq, hwirq;
140
141 /* We support MSI, but not MSI-X */
142 if (desc->msi_attrib.is_msix)
143 return -EINVAL;
144
145 hwirq = armada_370_xp_alloc_msi();
146 if (hwirq < 0)
147 return hwirq;
148
149 virq = irq_create_mapping(armada_370_xp_msi_domain, hwirq);
150 if (!virq) {
151 armada_370_xp_free_msi(hwirq);
152 return -EINVAL;
153 }
154
155 irq_set_msi_desc(virq, desc);
156
157 msg.address_lo = msi_doorbell_addr;
158 msg.address_hi = 0;
159 msg.data = 0xf00 | (hwirq + 16);
160
161 write_msi_msg(virq, &msg);
162 return 0;
163 }
164
armada_370_xp_teardown_msi_irq(struct msi_chip * chip,unsigned int irq)165 static void armada_370_xp_teardown_msi_irq(struct msi_chip *chip,
166 unsigned int irq)
167 {
168 struct irq_data *d = irq_get_irq_data(irq);
169 unsigned long hwirq = d->hwirq;
170
171 irq_dispose_mapping(irq);
172 armada_370_xp_free_msi(hwirq);
173 }
174
175 static struct irq_chip armada_370_xp_msi_irq_chip = {
176 .name = "armada_370_xp_msi_irq",
177 .irq_enable = unmask_msi_irq,
178 .irq_disable = mask_msi_irq,
179 .irq_mask = mask_msi_irq,
180 .irq_unmask = unmask_msi_irq,
181 };
182
armada_370_xp_msi_map(struct irq_domain * domain,unsigned int virq,irq_hw_number_t hw)183 static int armada_370_xp_msi_map(struct irq_domain *domain, unsigned int virq,
184 irq_hw_number_t hw)
185 {
186 irq_set_chip_and_handler(virq, &armada_370_xp_msi_irq_chip,
187 handle_simple_irq);
188 set_irq_flags(virq, IRQF_VALID);
189
190 return 0;
191 }
192
193 static const struct irq_domain_ops armada_370_xp_msi_irq_ops = {
194 .map = armada_370_xp_msi_map,
195 };
196
armada_370_xp_msi_init(struct device_node * node,phys_addr_t main_int_phys_base)197 static int armada_370_xp_msi_init(struct device_node *node,
198 phys_addr_t main_int_phys_base)
199 {
200 struct msi_chip *msi_chip;
201 u32 reg;
202 int ret;
203
204 msi_doorbell_addr = main_int_phys_base +
205 ARMADA_370_XP_SW_TRIG_INT_OFFS;
206
207 msi_chip = kzalloc(sizeof(*msi_chip), GFP_KERNEL);
208 if (!msi_chip)
209 return -ENOMEM;
210
211 msi_chip->setup_irq = armada_370_xp_setup_msi_irq;
212 msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq;
213 msi_chip->of_node = node;
214
215 armada_370_xp_msi_domain =
216 irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
217 &armada_370_xp_msi_irq_ops,
218 NULL);
219 if (!armada_370_xp_msi_domain) {
220 kfree(msi_chip);
221 return -ENOMEM;
222 }
223
224 ret = of_pci_msi_chip_add(msi_chip);
225 if (ret < 0) {
226 irq_domain_remove(armada_370_xp_msi_domain);
227 kfree(msi_chip);
228 return ret;
229 }
230
231 reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
232 | PCI_MSI_DOORBELL_MASK;
233
234 writel(reg, per_cpu_int_base +
235 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
236
237 /* Unmask IPI interrupt */
238 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
239
240 return 0;
241 }
242 #else
armada_370_xp_msi_init(struct device_node * node,phys_addr_t main_int_phys_base)243 static inline int armada_370_xp_msi_init(struct device_node *node,
244 phys_addr_t main_int_phys_base)
245 {
246 return 0;
247 }
248 #endif
249
250 #ifdef CONFIG_SMP
251 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
252
armada_xp_set_affinity(struct irq_data * d,const struct cpumask * mask_val,bool force)253 static int armada_xp_set_affinity(struct irq_data *d,
254 const struct cpumask *mask_val, bool force)
255 {
256 irq_hw_number_t hwirq = irqd_to_hwirq(d);
257 unsigned long reg, mask;
258 int cpu;
259
260 /* Select a single core from the affinity mask which is online */
261 cpu = cpumask_any_and(mask_val, cpu_online_mask);
262 mask = 1UL << cpu_logical_map(cpu);
263
264 raw_spin_lock(&irq_controller_lock);
265 reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
266 reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask;
267 writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
268 raw_spin_unlock(&irq_controller_lock);
269
270 return 0;
271 }
272 #endif
273
274 static struct irq_chip armada_370_xp_irq_chip = {
275 .name = "armada_370_xp_irq",
276 .irq_mask = armada_370_xp_irq_mask,
277 .irq_mask_ack = armada_370_xp_irq_mask,
278 .irq_unmask = armada_370_xp_irq_unmask,
279 #ifdef CONFIG_SMP
280 .irq_set_affinity = armada_xp_set_affinity,
281 #endif
282 };
283
armada_370_xp_mpic_irq_map(struct irq_domain * h,unsigned int virq,irq_hw_number_t hw)284 static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
285 unsigned int virq, irq_hw_number_t hw)
286 {
287 armada_370_xp_irq_mask(irq_get_irq_data(virq));
288 if (hw != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
289 writel(hw, per_cpu_int_base +
290 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
291 else
292 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
293 irq_set_status_flags(virq, IRQ_LEVEL);
294
295 if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) {
296 irq_set_percpu_devid(virq);
297 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
298 handle_percpu_devid_irq);
299
300 } else {
301 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
302 handle_level_irq);
303 }
304 set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
305
306 return 0;
307 }
308
309 #ifdef CONFIG_SMP
armada_mpic_send_doorbell(const struct cpumask * mask,unsigned int irq)310 static void armada_mpic_send_doorbell(const struct cpumask *mask,
311 unsigned int irq)
312 {
313 int cpu;
314 unsigned long map = 0;
315
316 /* Convert our logical CPU mask into a physical one. */
317 for_each_cpu(cpu, mask)
318 map |= 1 << cpu_logical_map(cpu);
319
320 /*
321 * Ensure that stores to Normal memory are visible to the
322 * other CPUs before issuing the IPI.
323 */
324 dsb();
325
326 /* submit softirq */
327 writel((map << 8) | irq, main_int_base +
328 ARMADA_370_XP_SW_TRIG_INT_OFFS);
329 }
330
armada_xp_mpic_smp_cpu_init(void)331 static void armada_xp_mpic_smp_cpu_init(void)
332 {
333 u32 control;
334 int nr_irqs, i;
335
336 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
337 nr_irqs = (control >> 2) & 0x3ff;
338
339 for (i = 0; i < nr_irqs; i++)
340 writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
341
342 /* Clear pending IPIs */
343 writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
344
345 /* Enable first 8 IPIs */
346 writel(IPI_DOORBELL_MASK, per_cpu_int_base +
347 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
348
349 /* Unmask IPI interrupt */
350 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
351 }
352
armada_xp_mpic_secondary_init(struct notifier_block * nfb,unsigned long action,void * hcpu)353 static int armada_xp_mpic_secondary_init(struct notifier_block *nfb,
354 unsigned long action, void *hcpu)
355 {
356 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
357 armada_xp_mpic_smp_cpu_init();
358
359 return NOTIFY_OK;
360 }
361
362 static struct notifier_block armada_370_xp_mpic_cpu_notifier = {
363 .notifier_call = armada_xp_mpic_secondary_init,
364 .priority = 100,
365 };
366
mpic_cascaded_secondary_init(struct notifier_block * nfb,unsigned long action,void * hcpu)367 static int mpic_cascaded_secondary_init(struct notifier_block *nfb,
368 unsigned long action, void *hcpu)
369 {
370 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
371 enable_percpu_irq(parent_irq, IRQ_TYPE_NONE);
372
373 return NOTIFY_OK;
374 }
375
376 static struct notifier_block mpic_cascaded_cpu_notifier = {
377 .notifier_call = mpic_cascaded_secondary_init,
378 .priority = 100,
379 };
380
381 #endif /* CONFIG_SMP */
382
383 static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
384 .map = armada_370_xp_mpic_irq_map,
385 .xlate = irq_domain_xlate_onecell,
386 };
387
388 #ifdef CONFIG_PCI_MSI
armada_370_xp_handle_msi_irq(struct pt_regs * regs,bool is_chained)389 static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
390 {
391 u32 msimask, msinr;
392
393 msimask = readl_relaxed(per_cpu_int_base +
394 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
395 & PCI_MSI_DOORBELL_MASK;
396
397 writel(~msimask, per_cpu_int_base +
398 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
399
400 for (msinr = PCI_MSI_DOORBELL_START;
401 msinr < PCI_MSI_DOORBELL_END; msinr++) {
402 int irq;
403
404 if (!(msimask & BIT(msinr)))
405 continue;
406
407 if (is_chained) {
408 irq = irq_find_mapping(armada_370_xp_msi_domain,
409 msinr - 16);
410 generic_handle_irq(irq);
411 } else {
412 irq = msinr - 16;
413 handle_domain_irq(armada_370_xp_msi_domain,
414 irq, regs);
415 }
416 }
417 }
418 #else
armada_370_xp_handle_msi_irq(struct pt_regs * r,bool b)419 static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
420 #endif
421
armada_370_xp_mpic_handle_cascade_irq(unsigned int irq,struct irq_desc * desc)422 static void armada_370_xp_mpic_handle_cascade_irq(unsigned int irq,
423 struct irq_desc *desc)
424 {
425 struct irq_chip *chip = irq_get_chip(irq);
426 unsigned long irqmap, irqn, irqsrc, cpuid;
427 unsigned int cascade_irq;
428
429 chained_irq_enter(chip, desc);
430
431 irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
432 cpuid = cpu_logical_map(smp_processor_id());
433
434 for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
435 irqsrc = readl_relaxed(main_int_base +
436 ARMADA_370_XP_INT_SOURCE_CTL(irqn));
437
438 /* Check if the interrupt is not masked on current CPU.
439 * Test IRQ (0-1) and FIQ (8-9) mask bits.
440 */
441 if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
442 continue;
443
444 if (irqn == 1) {
445 armada_370_xp_handle_msi_irq(NULL, true);
446 continue;
447 }
448
449 cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn);
450 generic_handle_irq(cascade_irq);
451 }
452
453 chained_irq_exit(chip, desc);
454 }
455
456 static void __exception_irq_entry
armada_370_xp_handle_irq(struct pt_regs * regs)457 armada_370_xp_handle_irq(struct pt_regs *regs)
458 {
459 u32 irqstat, irqnr;
460
461 do {
462 irqstat = readl_relaxed(per_cpu_int_base +
463 ARMADA_370_XP_CPU_INTACK_OFFS);
464 irqnr = irqstat & 0x3FF;
465
466 if (irqnr > 1022)
467 break;
468
469 if (irqnr > 1) {
470 handle_domain_irq(armada_370_xp_mpic_domain,
471 irqnr, regs);
472 continue;
473 }
474
475 /* MSI handling */
476 if (irqnr == 1)
477 armada_370_xp_handle_msi_irq(regs, false);
478
479 #ifdef CONFIG_SMP
480 /* IPI Handling */
481 if (irqnr == 0) {
482 u32 ipimask, ipinr;
483
484 ipimask = readl_relaxed(per_cpu_int_base +
485 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
486 & IPI_DOORBELL_MASK;
487
488 writel(~ipimask, per_cpu_int_base +
489 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
490
491 /* Handle all pending doorbells */
492 for (ipinr = IPI_DOORBELL_START;
493 ipinr < IPI_DOORBELL_END; ipinr++) {
494 if (ipimask & (0x1 << ipinr))
495 handle_IPI(ipinr, regs);
496 }
497 continue;
498 }
499 #endif
500
501 } while (1);
502 }
503
armada_370_xp_mpic_of_init(struct device_node * node,struct device_node * parent)504 static int __init armada_370_xp_mpic_of_init(struct device_node *node,
505 struct device_node *parent)
506 {
507 struct resource main_int_res, per_cpu_int_res;
508 int nr_irqs, i;
509 u32 control;
510
511 BUG_ON(of_address_to_resource(node, 0, &main_int_res));
512 BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));
513
514 BUG_ON(!request_mem_region(main_int_res.start,
515 resource_size(&main_int_res),
516 node->full_name));
517 BUG_ON(!request_mem_region(per_cpu_int_res.start,
518 resource_size(&per_cpu_int_res),
519 node->full_name));
520
521 main_int_base = ioremap(main_int_res.start,
522 resource_size(&main_int_res));
523 BUG_ON(!main_int_base);
524
525 per_cpu_int_base = ioremap(per_cpu_int_res.start,
526 resource_size(&per_cpu_int_res));
527 BUG_ON(!per_cpu_int_base);
528
529 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
530 nr_irqs = (control >> 2) & 0x3ff;
531
532 for (i = 0; i < nr_irqs; i++)
533 writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
534
535 armada_370_xp_mpic_domain =
536 irq_domain_add_linear(node, nr_irqs,
537 &armada_370_xp_mpic_irq_ops, NULL);
538
539 BUG_ON(!armada_370_xp_mpic_domain);
540
541 #ifdef CONFIG_SMP
542 armada_xp_mpic_smp_cpu_init();
543 #endif
544
545 armada_370_xp_msi_init(node, main_int_res.start);
546
547 parent_irq = irq_of_parse_and_map(node, 0);
548 if (parent_irq <= 0) {
549 irq_set_default_host(armada_370_xp_mpic_domain);
550 set_handle_irq(armada_370_xp_handle_irq);
551 #ifdef CONFIG_SMP
552 set_smp_cross_call(armada_mpic_send_doorbell);
553 register_cpu_notifier(&armada_370_xp_mpic_cpu_notifier);
554 #endif
555 } else {
556 #ifdef CONFIG_SMP
557 register_cpu_notifier(&mpic_cascaded_cpu_notifier);
558 #endif
559 irq_set_chained_handler(parent_irq,
560 armada_370_xp_mpic_handle_cascade_irq);
561 }
562
563 return 0;
564 }
565
566 IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);
567