1 /*
2 * MTD SPI driver for ST M25Pxx (and similar) serial flash chips
3 *
4 * Author: Mike Lavender, mike@steroidmicros.com
5 *
6 * Copyright (c) 2005, Intec Automation Inc.
7 *
8 * Some parts are based on lart.c by Abraham Van Der Merwe
9 *
10 * Cleaned up and generalized based on mtd_dataflash.c
11 *
12 * This code is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 */
17
18 #include <linux/err.h>
19 #include <linux/errno.h>
20 #include <linux/module.h>
21 #include <linux/device.h>
22
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/partitions.h>
25
26 #include <linux/spi/spi.h>
27 #include <linux/spi/flash.h>
28 #include <linux/mtd/spi-nor.h>
29
30 #define MAX_CMD_SIZE 6
31 struct m25p {
32 struct spi_device *spi;
33 struct spi_nor spi_nor;
34 struct mtd_info mtd;
35 u8 command[MAX_CMD_SIZE];
36 };
37
m25p80_read_reg(struct spi_nor * nor,u8 code,u8 * val,int len)38 static int m25p80_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
39 {
40 struct m25p *flash = nor->priv;
41 struct spi_device *spi = flash->spi;
42 int ret;
43
44 ret = spi_write_then_read(spi, &code, 1, val, len);
45 if (ret < 0)
46 dev_err(&spi->dev, "error %d reading %x\n", ret, code);
47
48 return ret;
49 }
50
m25p_addr2cmd(struct spi_nor * nor,unsigned int addr,u8 * cmd)51 static void m25p_addr2cmd(struct spi_nor *nor, unsigned int addr, u8 *cmd)
52 {
53 /* opcode is in cmd[0] */
54 cmd[1] = addr >> (nor->addr_width * 8 - 8);
55 cmd[2] = addr >> (nor->addr_width * 8 - 16);
56 cmd[3] = addr >> (nor->addr_width * 8 - 24);
57 cmd[4] = addr >> (nor->addr_width * 8 - 32);
58 }
59
m25p_cmdsz(struct spi_nor * nor)60 static int m25p_cmdsz(struct spi_nor *nor)
61 {
62 return 1 + nor->addr_width;
63 }
64
m25p80_write_reg(struct spi_nor * nor,u8 opcode,u8 * buf,int len,int wr_en)65 static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
66 int wr_en)
67 {
68 struct m25p *flash = nor->priv;
69 struct spi_device *spi = flash->spi;
70
71 flash->command[0] = opcode;
72 if (buf)
73 memcpy(&flash->command[1], buf, len);
74
75 return spi_write(spi, flash->command, len + 1);
76 }
77
m25p80_write(struct spi_nor * nor,loff_t to,size_t len,size_t * retlen,const u_char * buf)78 static void m25p80_write(struct spi_nor *nor, loff_t to, size_t len,
79 size_t *retlen, const u_char *buf)
80 {
81 struct m25p *flash = nor->priv;
82 struct spi_device *spi = flash->spi;
83 struct spi_transfer t[2] = {};
84 struct spi_message m;
85 int cmd_sz = m25p_cmdsz(nor);
86
87 spi_message_init(&m);
88
89 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
90 cmd_sz = 1;
91
92 flash->command[0] = nor->program_opcode;
93 m25p_addr2cmd(nor, to, flash->command);
94
95 t[0].tx_buf = flash->command;
96 t[0].len = cmd_sz;
97 spi_message_add_tail(&t[0], &m);
98
99 t[1].tx_buf = buf;
100 t[1].len = len;
101 spi_message_add_tail(&t[1], &m);
102
103 spi_sync(spi, &m);
104
105 *retlen += m.actual_length - cmd_sz;
106 }
107
m25p80_rx_nbits(struct spi_nor * nor)108 static inline unsigned int m25p80_rx_nbits(struct spi_nor *nor)
109 {
110 switch (nor->flash_read) {
111 case SPI_NOR_DUAL:
112 return 2;
113 case SPI_NOR_QUAD:
114 return 4;
115 default:
116 return 0;
117 }
118 }
119
120 /*
121 * Read an address range from the nor chip. The address range
122 * may be any size provided it is within the physical boundaries.
123 */
m25p80_read(struct spi_nor * nor,loff_t from,size_t len,size_t * retlen,u_char * buf)124 static int m25p80_read(struct spi_nor *nor, loff_t from, size_t len,
125 size_t *retlen, u_char *buf)
126 {
127 struct m25p *flash = nor->priv;
128 struct spi_device *spi = flash->spi;
129 struct spi_transfer t[2];
130 struct spi_message m;
131 int dummy = nor->read_dummy;
132 int ret;
133
134 /* Wait till previous write/erase is done. */
135 ret = nor->wait_till_ready(nor);
136 if (ret)
137 return ret;
138
139 spi_message_init(&m);
140 memset(t, 0, (sizeof t));
141
142 flash->command[0] = nor->read_opcode;
143 m25p_addr2cmd(nor, from, flash->command);
144
145 t[0].tx_buf = flash->command;
146 t[0].len = m25p_cmdsz(nor) + dummy;
147 spi_message_add_tail(&t[0], &m);
148
149 t[1].rx_buf = buf;
150 t[1].rx_nbits = m25p80_rx_nbits(nor);
151 t[1].len = len;
152 spi_message_add_tail(&t[1], &m);
153
154 spi_sync(spi, &m);
155
156 *retlen = m.actual_length - m25p_cmdsz(nor) - dummy;
157 return 0;
158 }
159
m25p80_erase(struct spi_nor * nor,loff_t offset)160 static int m25p80_erase(struct spi_nor *nor, loff_t offset)
161 {
162 struct m25p *flash = nor->priv;
163 int ret;
164
165 dev_dbg(nor->dev, "%dKiB at 0x%08x\n",
166 flash->mtd.erasesize / 1024, (u32)offset);
167
168 /* Wait until finished previous write command. */
169 ret = nor->wait_till_ready(nor);
170 if (ret)
171 return ret;
172
173 /* Send write enable, then erase commands. */
174 ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0);
175 if (ret)
176 return ret;
177
178 /* Set up command buffer. */
179 flash->command[0] = nor->erase_opcode;
180 m25p_addr2cmd(nor, offset, flash->command);
181
182 spi_write(flash->spi, flash->command, m25p_cmdsz(nor));
183
184 return 0;
185 }
186
187 /*
188 * board specific setup should have ensured the SPI clock used here
189 * matches what the READ command supports, at least until this driver
190 * understands FAST_READ (for clocks over 25 MHz).
191 */
m25p_probe(struct spi_device * spi)192 static int m25p_probe(struct spi_device *spi)
193 {
194 struct mtd_part_parser_data ppdata;
195 struct flash_platform_data *data;
196 struct m25p *flash;
197 struct spi_nor *nor;
198 enum read_mode mode = SPI_NOR_NORMAL;
199 char *flash_name = NULL;
200 int ret;
201
202 data = dev_get_platdata(&spi->dev);
203
204 flash = devm_kzalloc(&spi->dev, sizeof(*flash), GFP_KERNEL);
205 if (!flash)
206 return -ENOMEM;
207
208 nor = &flash->spi_nor;
209
210 /* install the hooks */
211 nor->read = m25p80_read;
212 nor->write = m25p80_write;
213 nor->erase = m25p80_erase;
214 nor->write_reg = m25p80_write_reg;
215 nor->read_reg = m25p80_read_reg;
216
217 nor->dev = &spi->dev;
218 nor->mtd = &flash->mtd;
219 nor->priv = flash;
220
221 spi_set_drvdata(spi, flash);
222 flash->mtd.priv = nor;
223 flash->spi = spi;
224
225 if (spi->mode & SPI_RX_QUAD)
226 mode = SPI_NOR_QUAD;
227 else if (spi->mode & SPI_RX_DUAL)
228 mode = SPI_NOR_DUAL;
229
230 if (data && data->name)
231 flash->mtd.name = data->name;
232
233 /* For some (historical?) reason many platforms provide two different
234 * names in flash_platform_data: "name" and "type". Quite often name is
235 * set to "m25p80" and then "type" provides a real chip name.
236 * If that's the case, respect "type" and ignore a "name".
237 */
238 if (data && data->type)
239 flash_name = data->type;
240 else
241 flash_name = spi->modalias;
242
243 ret = spi_nor_scan(nor, flash_name, mode);
244 if (ret)
245 return ret;
246
247 ppdata.of_node = spi->dev.of_node;
248
249 return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
250 data ? data->parts : NULL,
251 data ? data->nr_parts : 0);
252 }
253
254
m25p_remove(struct spi_device * spi)255 static int m25p_remove(struct spi_device *spi)
256 {
257 struct m25p *flash = spi_get_drvdata(spi);
258
259 /* Clean up MTD stuff. */
260 return mtd_device_unregister(&flash->mtd);
261 }
262
263
264 /*
265 * XXX This needs to be kept in sync with spi_nor_ids. We can't share
266 * it with spi-nor, because if this is built as a module then modpost
267 * won't be able to read it and add appropriate aliases.
268 */
269 static const struct spi_device_id m25p_ids[] = {
270 {"at25fs010"}, {"at25fs040"}, {"at25df041a"}, {"at25df321a"},
271 {"at25df641"}, {"at26f004"}, {"at26df081a"}, {"at26df161a"},
272 {"at26df321"}, {"at45db081d"},
273 {"en25f32"}, {"en25p32"}, {"en25q32b"}, {"en25p64"},
274 {"en25q64"}, {"en25qh128"}, {"en25qh256"},
275 {"f25l32pa"},
276 {"mr25h256"}, {"mr25h10"},
277 {"gd25q32"}, {"gd25q64"},
278 {"160s33b"}, {"320s33b"}, {"640s33b"},
279 {"mx25l2005a"}, {"mx25l4005a"}, {"mx25l8005"}, {"mx25l1606e"},
280 {"mx25l3205d"}, {"mx25l3255e"}, {"mx25l6405d"}, {"mx25l12805d"},
281 {"mx25l12855e"},{"mx25l25635e"},{"mx25l25655e"},{"mx66l51235l"},
282 {"mx66l1g55g"},
283 {"n25q064"}, {"n25q128a11"}, {"n25q128a13"}, {"n25q256a"},
284 {"n25q512a"}, {"n25q512ax3"}, {"n25q00"},
285 {"pm25lv512"}, {"pm25lv010"}, {"pm25lq032"},
286 {"s25sl032p"}, {"s25sl064p"}, {"s25fl256s0"}, {"s25fl256s1"},
287 {"s25fl512s"}, {"s70fl01gs"}, {"s25sl12800"}, {"s25sl12801"},
288 {"s25fl129p0"}, {"s25fl129p1"}, {"s25sl004a"}, {"s25sl008a"},
289 {"s25sl016a"}, {"s25sl032a"}, {"s25sl064a"}, {"s25fl008k"},
290 {"s25fl016k"}, {"s25fl064k"},
291 {"sst25vf040b"},{"sst25vf080b"},{"sst25vf016b"},{"sst25vf032b"},
292 {"sst25vf064c"},{"sst25wf512"}, {"sst25wf010"}, {"sst25wf020"},
293 {"sst25wf040"},
294 {"m25p05"}, {"m25p10"}, {"m25p20"}, {"m25p40"},
295 {"m25p80"}, {"m25p16"}, {"m25p32"}, {"m25p64"},
296 {"m25p128"}, {"n25q032"},
297 {"m25p05-nonjedec"}, {"m25p10-nonjedec"}, {"m25p20-nonjedec"},
298 {"m25p40-nonjedec"}, {"m25p80-nonjedec"}, {"m25p16-nonjedec"},
299 {"m25p32-nonjedec"}, {"m25p64-nonjedec"}, {"m25p128-nonjedec"},
300 {"m45pe10"}, {"m45pe80"}, {"m45pe16"},
301 {"m25pe20"}, {"m25pe80"}, {"m25pe16"},
302 {"m25px16"}, {"m25px32"}, {"m25px32-s0"}, {"m25px32-s1"},
303 {"m25px64"}, {"m25px80"},
304 {"w25x10"}, {"w25x20"}, {"w25x40"}, {"w25x80"},
305 {"w25x16"}, {"w25x32"}, {"w25q32"}, {"w25q32dw"},
306 {"w25x64"}, {"w25q64"}, {"w25q80"}, {"w25q80bl"},
307 {"w25q128"}, {"w25q256"}, {"cat25c11"},
308 {"cat25c03"}, {"cat25c09"}, {"cat25c17"}, {"cat25128"},
309 { },
310 };
311 MODULE_DEVICE_TABLE(spi, m25p_ids);
312
313
314 static struct spi_driver m25p80_driver = {
315 .driver = {
316 .name = "m25p80",
317 .owner = THIS_MODULE,
318 },
319 .id_table = m25p_ids,
320 .probe = m25p_probe,
321 .remove = m25p_remove,
322
323 /* REVISIT: many of these chips have deep power-down modes, which
324 * should clearly be entered on suspend() to minimize power use.
325 * And also when they're otherwise idle...
326 */
327 };
328
329 module_spi_driver(m25p80_driver);
330
331 MODULE_LICENSE("GPL");
332 MODULE_AUTHOR("Mike Lavender");
333 MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips");
334