1 /*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
8 #ifndef _QLCNIC_H_
9 #define _QLCNIC_H_
10
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
18 #include <linux/ip.h>
19 #include <linux/in.h>
20 #include <linux/tcp.h>
21 #include <linux/skbuff.h>
22 #include <linux/firmware.h>
23 #include <linux/ethtool.h>
24 #include <linux/mii.h>
25 #include <linux/timer.h>
26 #include <linux/irq.h>
27
28 #include <linux/vmalloc.h>
29
30 #include <linux/io.h>
31 #include <asm/byteorder.h>
32 #include <linux/bitops.h>
33 #include <linux/if_vlan.h>
34
35 #include "qlcnic_hdr.h"
36 #include "qlcnic_hw.h"
37 #include "qlcnic_83xx_hw.h"
38 #include "qlcnic_dcb.h"
39
40 #define _QLCNIC_LINUX_MAJOR 5
41 #define _QLCNIC_LINUX_MINOR 3
42 #define _QLCNIC_LINUX_SUBVERSION 62
43 #define QLCNIC_LINUX_VERSIONID "5.3.62"
44 #define QLCNIC_DRV_IDC_VER 0x01
45 #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\
46 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION))
47
48 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
49 #define _major(v) (((v) >> 24) & 0xff)
50 #define _minor(v) (((v) >> 16) & 0xff)
51 #define _build(v) ((v) & 0xffff)
52
53 /* version in image has weird encoding:
54 * 7:0 - major
55 * 15:8 - minor
56 * 31:16 - build (little endian)
57 */
58 #define QLCNIC_DECODE_VERSION(v) \
59 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
60
61 #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2)
62 #define QLCNIC_NUM_FLASH_SECTORS (64)
63 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
64 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \
65 * QLCNIC_FLASH_SECTOR_SIZE)
66
67 #define RCV_DESC_RINGSIZE(rds_ring) \
68 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
69 #define RCV_BUFF_RINGSIZE(rds_ring) \
70 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
71 #define STATUS_DESC_RINGSIZE(sds_ring) \
72 (sizeof(struct status_desc) * (sds_ring)->num_desc)
73 #define TX_BUFF_RINGSIZE(tx_ring) \
74 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
75 #define TX_DESC_RINGSIZE(tx_ring) \
76 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
77
78 #define QLCNIC_P3P_A0 0x50
79 #define QLCNIC_P3P_C0 0x58
80
81 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0)
82
83 #define FIRST_PAGE_GROUP_START 0
84 #define FIRST_PAGE_GROUP_END 0x100000
85
86 #define P3P_MAX_MTU (9600)
87 #define P3P_MIN_MTU (68)
88 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */
89
90 #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
91 #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU)
92 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048
93 #define QLCNIC_LRO_BUFFER_EXTRA 2048
94
95 /* Tx defines */
96 #define QLCNIC_MAX_FRAGS_PER_TX 14
97 #define MAX_TSO_HEADER_DESC 2
98 #define MGMT_CMD_DESC_RESV 4
99 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
100 + MGMT_CMD_DESC_RESV)
101 #define QLCNIC_MAX_TX_TIMEOUTS 2
102
103 /* Driver will use 1 Tx ring in INT-x/MSI/SRIOV mode. */
104 #define QLCNIC_SINGLE_RING 1
105 #define QLCNIC_DEF_SDS_RINGS 4
106 #define QLCNIC_DEF_TX_RINGS 4
107 #define QLCNIC_MAX_VNIC_TX_RINGS 4
108 #define QLCNIC_MAX_VNIC_SDS_RINGS 4
109 #define QLCNIC_83XX_MINIMUM_VECTOR 3
110 #define QLCNIC_82XX_MINIMUM_VECTOR 2
111
112 enum qlcnic_queue_type {
113 QLCNIC_TX_QUEUE = 1,
114 QLCNIC_RX_QUEUE,
115 };
116
117 /* Operational mode for driver */
118 #define QLCNIC_VNIC_MODE 0xFF
119 #define QLCNIC_DEFAULT_MODE 0x0
120
121 /* Virtual NIC function count */
122 #define QLC_DEFAULT_VNIC_COUNT 8
123 #define QLC_84XX_VNIC_COUNT 16
124
125 /*
126 * Following are the states of the Phantom. Phantom will set them and
127 * Host will read to check if the fields are correct.
128 */
129 #define PHAN_INITIALIZE_FAILED 0xffff
130 #define PHAN_INITIALIZE_COMPLETE 0xff01
131
132 /* Host writes the following to notify that it has done the init-handshake */
133 #define PHAN_INITIALIZE_ACK 0xf00f
134 #define PHAN_PEG_RCV_INITIALIZED 0xff01
135
136 #define NUM_RCV_DESC_RINGS 3
137
138 #define RCV_RING_NORMAL 0
139 #define RCV_RING_JUMBO 1
140
141 #define MIN_CMD_DESCRIPTORS 64
142 #define MIN_RCV_DESCRIPTORS 64
143 #define MIN_JUMBO_DESCRIPTORS 32
144
145 #define MAX_CMD_DESCRIPTORS 1024
146 #define MAX_RCV_DESCRIPTORS_1G 4096
147 #define MAX_RCV_DESCRIPTORS_10G 8192
148 #define MAX_RCV_DESCRIPTORS_VF 2048
149 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
150 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
151
152 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
153 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
154 #define DEFAULT_RCV_DESCRIPTORS_VF 1024
155 #define MAX_RDS_RINGS 2
156
157 #define get_next_index(index, length) \
158 (((index) + 1) & ((length) - 1))
159
160 /*
161 * Following data structures describe the descriptors that will be used.
162 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
163 * we are doing LSO (above the 1500 size packet) only.
164 */
165 struct cmd_desc_type0 {
166 u8 tcp_hdr_offset; /* For LSO only */
167 u8 ip_hdr_offset; /* For LSO only */
168 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
169 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
170
171 __le64 addr_buffer2;
172
173 __le16 encap_descr; /* 15:10 offset of outer L3 header,
174 * 9:6 number of 32bit words in outer L3 header,
175 * 5 offload outer L4 checksum,
176 * 4 offload outer L3 checksum,
177 * 3 Inner L4 type, TCP=0, UDP=1,
178 * 2 Inner L3 type, IPv4=0, IPv6=1,
179 * 1 Outer L3 type,IPv4=0, IPv6=1,
180 * 0 type of encapsulation, GRE=0, VXLAN=1
181 */
182 __le16 mss;
183 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
184 u8 hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
185 u8 outer_hdr_length; /* Encapsulation only */
186 u8 rsvd1;
187
188 __le64 addr_buffer3;
189 __le64 addr_buffer1;
190
191 __le16 buffer_length[4];
192
193 __le64 addr_buffer4;
194
195 u8 eth_addr[ETH_ALEN];
196 __le16 vlan_TCI; /* In case of encapsulation,
197 * this is for outer VLAN
198 */
199
200 } __attribute__ ((aligned(64)));
201
202 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
203 struct rcv_desc {
204 __le16 reference_handle;
205 __le16 reserved;
206 __le32 buffer_length; /* allocated buffer length (usually 2K) */
207 __le64 addr_buffer;
208 } __packed;
209
210 struct status_desc {
211 __le64 status_desc_data[2];
212 } __attribute__ ((aligned(16)));
213
214 /* UNIFIED ROMIMAGE */
215 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000
216 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
217 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6
218 #define QLCNIC_UNI_DIR_SECT_FW 0x7
219
220 /*Offsets */
221 #define QLCNIC_UNI_CHIP_REV_OFF 10
222 #define QLCNIC_UNI_FLAGS_OFF 11
223 #define QLCNIC_UNI_BIOS_VERSION_OFF 12
224 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27
225 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29
226
227 struct uni_table_desc{
228 __le32 findex;
229 __le32 num_entries;
230 __le32 entry_size;
231 __le32 reserved[5];
232 };
233
234 struct uni_data_desc{
235 __le32 findex;
236 __le32 size;
237 __le32 reserved[5];
238 };
239
240 /* Flash Defines and Structures */
241 #define QLCNIC_FLT_LOCATION 0x3F1000
242 #define QLCNIC_FDT_LOCATION 0x3F0000
243 #define QLCNIC_B0_FW_IMAGE_REGION 0x74
244 #define QLCNIC_C0_FW_IMAGE_REGION 0x97
245 #define QLCNIC_BOOTLD_REGION 0X72
246 struct qlcnic_flt_header {
247 u16 version;
248 u16 len;
249 u16 checksum;
250 u16 reserved;
251 };
252
253 struct qlcnic_flt_entry {
254 u8 region;
255 u8 reserved0;
256 u8 attrib;
257 u8 reserved1;
258 u32 size;
259 u32 start_addr;
260 u32 end_addr;
261 };
262
263 /* Flash Descriptor Table */
264 struct qlcnic_fdt {
265 u32 valid;
266 u16 ver;
267 u16 len;
268 u16 cksum;
269 u16 unused;
270 u8 model[16];
271 u8 mfg_id;
272 u16 id;
273 u8 flag;
274 u8 erase_cmd;
275 u8 alt_erase_cmd;
276 u8 write_enable_cmd;
277 u8 write_enable_bits;
278 u8 write_statusreg_cmd;
279 u8 unprotected_sec_cmd;
280 u8 read_manuf_cmd;
281 u32 block_size;
282 u32 alt_block_size;
283 u32 flash_size;
284 u32 write_enable_data;
285 u8 readid_addr_len;
286 u8 write_disable_bits;
287 u8 read_dev_id_len;
288 u8 chip_erase_cmd;
289 u16 read_timeo;
290 u8 protected_sec_cmd;
291 u8 resvd[65];
292 };
293 /* Magic number to let user know flash is programmed */
294 #define QLCNIC_BDINFO_MAGIC 0x12345678
295
296 #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021
297 #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022
298 #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023
299 #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024
300 #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025
301 #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026
302 #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027
303 #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028
304 #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029
305 #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a
306 #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b
307 #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031
308 #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032
309 #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080
310
311 #define QLCNIC_MSIX_TABLE_OFFSET 0x44
312
313 /* Flash memory map */
314 #define QLCNIC_BRDCFG_START 0x4000 /* board config */
315 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */
316 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */
317 #define QLCNIC_USER_START 0x3E8000 /* Firmare info */
318
319 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408)
320 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c)
321 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c)
322 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c)
323
324 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8)
325 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128)
326
327 #define QLCNIC_FW_MIN_SIZE (0x3fffff)
328 #define QLCNIC_UNIFIED_ROMIMAGE 0
329 #define QLCNIC_FLASH_ROMIMAGE 1
330 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff
331
332 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
333 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash"
334
335 extern char qlcnic_driver_name[];
336
337 extern int qlcnic_use_msi;
338 extern int qlcnic_use_msi_x;
339 extern int qlcnic_auto_fw_reset;
340 extern int qlcnic_load_fw_file;
341
342 /* Number of status descriptors to handle per interrupt */
343 #define MAX_STATUS_HANDLE (64)
344
345 /*
346 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This
347 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}.
348 */
349 struct qlcnic_skb_frag {
350 u64 dma;
351 u64 length;
352 };
353
354 /* Following defines are for the state of the buffers */
355 #define QLCNIC_BUFFER_FREE 0
356 #define QLCNIC_BUFFER_BUSY 1
357
358 /*
359 * There will be one qlcnic_buffer per skb packet. These will be
360 * used to save the dma info for pci_unmap_page()
361 */
362 struct qlcnic_cmd_buffer {
363 struct sk_buff *skb;
364 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1];
365 u32 frag_count;
366 };
367
368 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
369 struct qlcnic_rx_buffer {
370 u16 ref_handle;
371 struct sk_buff *skb;
372 struct list_head list;
373 u64 dma;
374 };
375
376 /* Board types */
377 #define QLCNIC_GBE 0x01
378 #define QLCNIC_XGBE 0x02
379
380 /*
381 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
382 * adjusted based on configured MTU.
383 */
384 #define QLCNIC_INTR_COAL_TYPE_RX 1
385 #define QLCNIC_INTR_COAL_TYPE_TX 2
386 #define QLCNIC_INTR_COAL_TYPE_RX_TX 3
387
388 #define QLCNIC_DEF_INTR_COALESCE_RX_TIME_US 3
389 #define QLCNIC_DEF_INTR_COALESCE_RX_PACKETS 256
390
391 #define QLCNIC_DEF_INTR_COALESCE_TX_TIME_US 64
392 #define QLCNIC_DEF_INTR_COALESCE_TX_PACKETS 64
393
394 #define QLCNIC_INTR_DEFAULT 0x04
395 #define QLCNIC_CONFIG_INTR_COALESCE 3
396 #define QLCNIC_DEV_INFO_SIZE 2
397
398 struct qlcnic_nic_intr_coalesce {
399 u8 type;
400 u8 sts_ring_mask;
401 u16 rx_packets;
402 u16 rx_time_us;
403 u16 tx_packets;
404 u16 tx_time_us;
405 u16 flag;
406 u32 timer_out;
407 };
408
409 struct qlcnic_83xx_dump_template_hdr {
410 u32 type;
411 u32 offset;
412 u32 size;
413 u32 cap_mask;
414 u32 num_entries;
415 u32 version;
416 u32 timestamp;
417 u32 checksum;
418 u32 drv_cap_mask;
419 u32 sys_info[3];
420 u32 saved_state[16];
421 u32 cap_sizes[8];
422 u32 ocm_wnd_reg[16];
423 u32 rsvd[0];
424 };
425
426 struct qlcnic_82xx_dump_template_hdr {
427 u32 type;
428 u32 offset;
429 u32 size;
430 u32 cap_mask;
431 u32 num_entries;
432 u32 version;
433 u32 timestamp;
434 u32 checksum;
435 u32 drv_cap_mask;
436 u32 sys_info[3];
437 u32 saved_state[16];
438 u32 cap_sizes[8];
439 u32 rsvd[7];
440 u32 capabilities;
441 u32 rsvd1[0];
442 };
443
444 #define QLC_PEX_DMA_READ_SIZE (PAGE_SIZE * 16)
445
446 struct qlcnic_fw_dump {
447 u8 clr; /* flag to indicate if dump is cleared */
448 bool enable; /* enable/disable dump */
449 u32 size; /* total size of the dump */
450 u32 cap_mask; /* Current capture mask */
451 void *data; /* dump data area */
452 void *tmpl_hdr;
453 dma_addr_t phys_addr;
454 void *dma_buffer;
455 bool use_pex_dma;
456 /* Read only elements which are common between 82xx and 83xx
457 * template header. Update these values immediately after we read
458 * template header from Firmware
459 */
460 u32 tmpl_hdr_size;
461 u32 version;
462 u32 num_entries;
463 u32 offset;
464 };
465
466 /*
467 * One hardware_context{} per adapter
468 * contains interrupt info as well shared hardware info.
469 */
470 struct qlcnic_hardware_context {
471 void __iomem *pci_base0;
472 void __iomem *ocm_win_crb;
473
474 unsigned long pci_len0;
475
476 rwlock_t crb_lock;
477 struct mutex mem_lock;
478
479 u8 revision_id;
480 u8 pci_func;
481 u8 linkup;
482 u8 loopback_state;
483 u8 beacon_state;
484 u8 has_link_events;
485 u8 fw_type;
486 u8 physical_port;
487 u8 reset_context;
488 u8 msix_supported;
489 u8 max_mac_filters;
490 u8 mc_enabled;
491 u8 max_mc_count;
492 u8 diag_test;
493 u8 num_msix;
494 u8 nic_mode;
495 int diag_cnt;
496
497 u16 max_uc_count;
498 u16 port_type;
499 u16 board_type;
500 u16 supported_type;
501
502 u16 link_speed;
503 u16 link_duplex;
504 u16 link_autoneg;
505 u16 module_type;
506
507 u16 op_mode;
508 u16 switch_mode;
509 u16 max_tx_ques;
510 u16 max_rx_ques;
511 u16 max_mtu;
512 u32 msg_enable;
513 u16 total_nic_func;
514 u16 max_pci_func;
515 u32 max_vnic_func;
516 u32 total_pci_func;
517
518 u32 capabilities;
519 u32 extra_capability[3];
520 u32 temp;
521 u32 int_vec_bit;
522 u32 fw_hal_version;
523 u32 port_config;
524 struct qlcnic_hardware_ops *hw_ops;
525 struct qlcnic_nic_intr_coalesce coal;
526 struct qlcnic_fw_dump fw_dump;
527 struct qlcnic_fdt fdt;
528 struct qlc_83xx_reset reset;
529 struct qlc_83xx_idc idc;
530 struct qlc_83xx_fw_info *fw_info;
531 struct qlcnic_intrpt_config *intr_tbl;
532 struct qlcnic_sriov *sriov;
533 u32 *reg_tbl;
534 u32 *ext_reg_tbl;
535 u32 mbox_aen[QLC_83XX_MBX_AEN_CNT];
536 u32 mbox_reg[4];
537 struct qlcnic_mailbox *mailbox;
538 u8 extend_lb_time;
539 u8 phys_port_id[ETH_ALEN];
540 u8 lb_mode;
541 u16 vxlan_port;
542 struct device *hwmon_dev;
543 u32 post_mode;
544 bool run_post;
545 };
546
547 struct qlcnic_adapter_stats {
548 u64 xmitcalled;
549 u64 xmitfinished;
550 u64 rxdropped;
551 u64 txdropped;
552 u64 csummed;
553 u64 rx_pkts;
554 u64 lro_pkts;
555 u64 rxbytes;
556 u64 txbytes;
557 u64 lrobytes;
558 u64 lso_frames;
559 u64 encap_lso_frames;
560 u64 encap_tx_csummed;
561 u64 encap_rx_csummed;
562 u64 xmit_on;
563 u64 xmit_off;
564 u64 skb_alloc_failure;
565 u64 null_rxbuf;
566 u64 rx_dma_map_error;
567 u64 tx_dma_map_error;
568 u64 spurious_intr;
569 u64 mac_filter_limit_overrun;
570 u64 mbx_spurious_intr;
571 };
572
573 /*
574 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
575 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
576 */
577 struct qlcnic_host_rds_ring {
578 void __iomem *crb_rcv_producer;
579 struct rcv_desc *desc_head;
580 struct qlcnic_rx_buffer *rx_buf_arr;
581 u32 num_desc;
582 u32 producer;
583 u32 dma_size;
584 u32 skb_size;
585 u32 flags;
586 struct list_head free_list;
587 spinlock_t lock;
588 dma_addr_t phys_addr;
589 } ____cacheline_internodealigned_in_smp;
590
591 struct qlcnic_host_sds_ring {
592 u32 consumer;
593 u32 num_desc;
594 void __iomem *crb_sts_consumer;
595
596 struct qlcnic_host_tx_ring *tx_ring;
597 struct status_desc *desc_head;
598 struct qlcnic_adapter *adapter;
599 struct napi_struct napi;
600 struct list_head free_list[NUM_RCV_DESC_RINGS];
601
602 void __iomem *crb_intr_mask;
603 int irq;
604
605 dma_addr_t phys_addr;
606 char name[IFNAMSIZ + 12];
607 } ____cacheline_internodealigned_in_smp;
608
609 struct qlcnic_tx_queue_stats {
610 u64 xmit_on;
611 u64 xmit_off;
612 u64 xmit_called;
613 u64 xmit_finished;
614 u64 tx_bytes;
615 };
616
617 struct qlcnic_host_tx_ring {
618 int irq;
619 void __iomem *crb_intr_mask;
620 char name[IFNAMSIZ + 12];
621 u16 ctx_id;
622
623 u32 state;
624 u32 producer;
625 u32 sw_consumer;
626 u32 num_desc;
627
628 struct qlcnic_tx_queue_stats tx_stats;
629
630 void __iomem *crb_cmd_producer;
631 struct cmd_desc_type0 *desc_head;
632 struct qlcnic_adapter *adapter;
633 struct napi_struct napi;
634 struct qlcnic_cmd_buffer *cmd_buf_arr;
635 __le32 *hw_consumer;
636
637 dma_addr_t phys_addr;
638 dma_addr_t hw_cons_phys_addr;
639 struct netdev_queue *txq;
640 /* Lock to protect Tx descriptors cleanup */
641 spinlock_t tx_clean_lock;
642 } ____cacheline_internodealigned_in_smp;
643
644 /*
645 * Receive context. There is one such structure per instance of the
646 * receive processing. Any state information that is relevant to
647 * the receive, and is must be in this structure. The global data may be
648 * present elsewhere.
649 */
650 struct qlcnic_recv_context {
651 struct qlcnic_host_rds_ring *rds_rings;
652 struct qlcnic_host_sds_ring *sds_rings;
653 u32 state;
654 u16 context_id;
655 u16 virt_port;
656 };
657
658 /* HW context creation */
659
660 #define QLCNIC_OS_CRB_RETRY_COUNT 4000
661
662 #define QLCNIC_CDRP_CMD_BIT 0x80000000
663
664 /*
665 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared
666 * in the crb QLCNIC_CDRP_CRB_OFFSET.
667 */
668 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp)
669 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
670
671 #define QLCNIC_CDRP_RSP_OK 0x00000001
672 #define QLCNIC_CDRP_RSP_FAIL 0x00000002
673 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003
674
675 /*
676 * All commands must have the QLCNIC_CDRP_CMD_BIT set in
677 * the crb QLCNIC_CDRP_CRB_OFFSET.
678 */
679 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd))
680
681 #define QLCNIC_RCODE_SUCCESS 0
682 #define QLCNIC_RCODE_INVALID_ARGS 6
683 #define QLCNIC_RCODE_NOT_SUPPORTED 9
684 #define QLCNIC_RCODE_NOT_PERMITTED 10
685 #define QLCNIC_RCODE_NOT_IMPL 15
686 #define QLCNIC_RCODE_INVALID 16
687 #define QLCNIC_RCODE_TIMEOUT 17
688 #define QLCNIC_DESTROY_CTX_RESET 0
689
690 /*
691 * Capabilities Announced
692 */
693 #define QLCNIC_CAP0_LEGACY_CONTEXT (1)
694 #define QLCNIC_CAP0_LEGACY_MN (1 << 2)
695 #define QLCNIC_CAP0_LSO (1 << 6)
696 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7)
697 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8)
698 #define QLCNIC_CAP0_VALIDOFF (1 << 11)
699 #define QLCNIC_CAP0_LRO_MSS (1 << 21)
700 #define QLCNIC_CAP0_TX_MULTI (1 << 22)
701
702 /*
703 * Context state
704 */
705 #define QLCNIC_HOST_CTX_STATE_FREED 0
706 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2
707
708 /*
709 * Rx context
710 */
711
712 struct qlcnic_hostrq_sds_ring {
713 __le64 host_phys_addr; /* Ring base addr */
714 __le32 ring_size; /* Ring entries */
715 __le16 msi_index;
716 __le16 rsvd; /* Padding */
717 } __packed;
718
719 struct qlcnic_hostrq_rds_ring {
720 __le64 host_phys_addr; /* Ring base addr */
721 __le64 buff_size; /* Packet buffer size */
722 __le32 ring_size; /* Ring entries */
723 __le32 ring_kind; /* Class of ring */
724 } __packed;
725
726 struct qlcnic_hostrq_rx_ctx {
727 __le64 host_rsp_dma_addr; /* Response dma'd here */
728 __le32 capabilities[4]; /* Flag bit vector */
729 __le32 host_int_crb_mode; /* Interrupt crb usage */
730 __le32 host_rds_crb_mode; /* RDS crb usage */
731 /* These ring offsets are relative to data[0] below */
732 __le32 rds_ring_offset; /* Offset to RDS config */
733 __le32 sds_ring_offset; /* Offset to SDS config */
734 __le16 num_rds_rings; /* Count of RDS rings */
735 __le16 num_sds_rings; /* Count of SDS rings */
736 __le16 valid_field_offset;
737 u8 txrx_sds_binding;
738 u8 msix_handler;
739 u8 reserved[128]; /* reserve space for future expansion*/
740 /* MUST BE 64-bit aligned.
741 The following is packed:
742 - N hostrq_rds_rings
743 - N hostrq_sds_rings */
744 char data[0];
745 } __packed;
746
747 struct qlcnic_cardrsp_rds_ring{
748 __le32 host_producer_crb; /* Crb to use */
749 __le32 rsvd1; /* Padding */
750 } __packed;
751
752 struct qlcnic_cardrsp_sds_ring {
753 __le32 host_consumer_crb; /* Crb to use */
754 __le32 interrupt_crb; /* Crb to use */
755 } __packed;
756
757 struct qlcnic_cardrsp_rx_ctx {
758 /* These ring offsets are relative to data[0] below */
759 __le32 rds_ring_offset; /* Offset to RDS config */
760 __le32 sds_ring_offset; /* Offset to SDS config */
761 __le32 host_ctx_state; /* Starting State */
762 __le32 num_fn_per_port; /* How many PCI fn share the port */
763 __le16 num_rds_rings; /* Count of RDS rings */
764 __le16 num_sds_rings; /* Count of SDS rings */
765 __le16 context_id; /* Handle for context */
766 u8 phys_port; /* Physical id of port */
767 u8 virt_port; /* Virtual/Logical id of port */
768 u8 reserved[128]; /* save space for future expansion */
769 /* MUST BE 64-bit aligned.
770 The following is packed:
771 - N cardrsp_rds_rings
772 - N cardrs_sds_rings */
773 char data[0];
774 } __packed;
775
776 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
777 (sizeof(HOSTRQ_RX) + \
778 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \
779 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))
780
781 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
782 (sizeof(CARDRSP_RX) + \
783 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \
784 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))
785
786 /*
787 * Tx context
788 */
789
790 struct qlcnic_hostrq_cds_ring {
791 __le64 host_phys_addr; /* Ring base addr */
792 __le32 ring_size; /* Ring entries */
793 __le32 rsvd; /* Padding */
794 } __packed;
795
796 struct qlcnic_hostrq_tx_ctx {
797 __le64 host_rsp_dma_addr; /* Response dma'd here */
798 __le64 cmd_cons_dma_addr; /* */
799 __le64 dummy_dma_addr; /* */
800 __le32 capabilities[4]; /* Flag bit vector */
801 __le32 host_int_crb_mode; /* Interrupt crb usage */
802 __le32 rsvd1; /* Padding */
803 __le16 rsvd2; /* Padding */
804 __le16 interrupt_ctl;
805 __le16 msi_index;
806 __le16 rsvd3; /* Padding */
807 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */
808 u8 reserved[128]; /* future expansion */
809 } __packed;
810
811 struct qlcnic_cardrsp_cds_ring {
812 __le32 host_producer_crb; /* Crb to use */
813 __le32 interrupt_crb; /* Crb to use */
814 } __packed;
815
816 struct qlcnic_cardrsp_tx_ctx {
817 __le32 host_ctx_state; /* Starting state */
818 __le16 context_id; /* Handle for context */
819 u8 phys_port; /* Physical id of port */
820 u8 virt_port; /* Virtual/Logical id of port */
821 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */
822 u8 reserved[128]; /* future expansion */
823 } __packed;
824
825 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
826 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
827
828 /* CRB */
829
830 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
831 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1
832 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2
833 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3
834
835 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
836 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1
837 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2
838 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3
839 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4
840
841
842 /* MAC */
843
844 #define MC_COUNT_P3P 38
845
846 #define QLCNIC_MAC_NOOP 0
847 #define QLCNIC_MAC_ADD 1
848 #define QLCNIC_MAC_DEL 2
849 #define QLCNIC_MAC_VLAN_ADD 3
850 #define QLCNIC_MAC_VLAN_DEL 4
851
852 struct qlcnic_mac_vlan_list {
853 struct list_head list;
854 uint8_t mac_addr[ETH_ALEN+2];
855 u16 vlan_id;
856 };
857
858 /* MAC Learn */
859 #define NO_MAC_LEARN 0
860 #define DRV_MAC_LEARN 1
861 #define FDB_MAC_LEARN 2
862
863 #define QLCNIC_HOST_REQUEST 0x13
864 #define QLCNIC_REQUEST 0x14
865
866 #define QLCNIC_MAC_EVENT 0x1
867
868 #define QLCNIC_IP_UP 2
869 #define QLCNIC_IP_DOWN 3
870
871 #define QLCNIC_ILB_MODE 0x1
872 #define QLCNIC_ELB_MODE 0x2
873 #define QLCNIC_LB_MODE_MASK 0x3
874
875 #define QLCNIC_LINKEVENT 0x1
876 #define QLCNIC_LB_RESPONSE 0x2
877 #define QLCNIC_IS_LB_CONFIGURED(VAL) \
878 (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE))
879
880 /*
881 * Driver --> Firmware
882 */
883 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1
884 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3
885 #define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4
886 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7
887 #define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc
888 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12
889
890 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15
891 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17
892 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18
893 #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 0x13
894
895 /*
896 * Firmware --> Driver
897 */
898
899 #define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK 0x8f
900 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 0x8D
901 #define QLCNIC_C2H_OPCODE_GET_DCB_AEN 0x90
902
903 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
904 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
905 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
906
907 #define QLCNIC_LRO_REQUEST_CLEANUP 4
908
909 /* Capabilites received */
910 #define QLCNIC_FW_CAPABILITY_TSO BIT_1
911 #define QLCNIC_FW_CAPABILITY_BDG BIT_8
912 #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9
913 #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10
914 #define QLCNIC_FW_CAPABILITY_2_MULTI_TX BIT_4
915 #define QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK BIT_27
916 #define QLCNIC_FW_CAPABILITY_MORE_CAPS BIT_31
917
918 #define QLCNIC_FW_CAPABILITY_2_LRO_MAX_TCP_SEG BIT_2
919 #define QLCNIC_FW_CAP2_HW_LRO_IPV6 BIT_3
920 #define QLCNIC_FW_CAPABILITY_SET_DRV_VER BIT_5
921 #define QLCNIC_FW_CAPABILITY_2_BEACON BIT_7
922 #define QLCNIC_FW_CAPABILITY_2_PER_PORT_ESWITCH_CFG BIT_9
923
924 #define QLCNIC_83XX_FW_CAPAB_ENCAP_RX_OFFLOAD BIT_0
925 #define QLCNIC_83XX_FW_CAPAB_ENCAP_TX_OFFLOAD BIT_1
926 #define QLCNIC_83XX_FW_CAPAB_ENCAP_CKO_OFFLOAD BIT_4
927
928 /* module types */
929 #define LINKEVENT_MODULE_NOT_PRESENT 1
930 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
931 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
932 #define LINKEVENT_MODULE_OPTICAL_LRM 4
933 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
934 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
935 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
936 #define LINKEVENT_MODULE_TWINAX 8
937
938 #define LINKSPEED_10GBPS 10000
939 #define LINKSPEED_1GBPS 1000
940 #define LINKSPEED_100MBPS 100
941 #define LINKSPEED_10MBPS 10
942
943 #define LINKSPEED_ENCODED_10MBPS 0
944 #define LINKSPEED_ENCODED_100MBPS 1
945 #define LINKSPEED_ENCODED_1GBPS 2
946
947 #define LINKEVENT_AUTONEG_DISABLED 0
948 #define LINKEVENT_AUTONEG_ENABLED 1
949
950 #define LINKEVENT_HALF_DUPLEX 0
951 #define LINKEVENT_FULL_DUPLEX 1
952
953 #define LINKEVENT_LINKSPEED_MBPS 0
954 #define LINKEVENT_LINKSPEED_ENCODED 1
955
956 /* firmware response header:
957 * 63:58 - message type
958 * 57:56 - owner
959 * 55:53 - desc count
960 * 52:48 - reserved
961 * 47:40 - completion id
962 * 39:32 - opcode
963 * 31:16 - error code
964 * 15:00 - reserved
965 */
966 #define qlcnic_get_nic_msg_opcode(msg_hdr) \
967 ((msg_hdr >> 32) & 0xFF)
968
969 struct qlcnic_fw_msg {
970 union {
971 struct {
972 u64 hdr;
973 u64 body[7];
974 };
975 u64 words[8];
976 };
977 };
978
979 struct qlcnic_nic_req {
980 __le64 qhdr;
981 __le64 req_hdr;
982 __le64 words[6];
983 } __packed;
984
985 struct qlcnic_mac_req {
986 u8 op;
987 u8 tag;
988 u8 mac_addr[6];
989 };
990
991 struct qlcnic_vlan_req {
992 __le16 vlan_id;
993 __le16 rsvd[3];
994 } __packed;
995
996 struct qlcnic_ipaddr {
997 __be32 ipv4;
998 __be32 ipv6[4];
999 };
1000
1001 #define QLCNIC_MSI_ENABLED 0x02
1002 #define QLCNIC_MSIX_ENABLED 0x04
1003 #define QLCNIC_LRO_ENABLED 0x01
1004 #define QLCNIC_LRO_DISABLED 0x00
1005 #define QLCNIC_BRIDGE_ENABLED 0X10
1006 #define QLCNIC_DIAG_ENABLED 0x20
1007 #define QLCNIC_ESWITCH_ENABLED 0x40
1008 #define QLCNIC_ADAPTER_INITIALIZED 0x80
1009 #define QLCNIC_TAGGING_ENABLED 0x100
1010 #define QLCNIC_MACSPOOF 0x200
1011 #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400
1012 #define QLCNIC_PROMISC_DISABLED 0x800
1013 #define QLCNIC_NEED_FLR 0x1000
1014 #define QLCNIC_FW_RESET_OWNER 0x2000
1015 #define QLCNIC_FW_HANG 0x4000
1016 #define QLCNIC_FW_LRO_MSS_CAP 0x8000
1017 #define QLCNIC_TX_INTR_SHARED 0x10000
1018 #define QLCNIC_APP_CHANGED_FLAGS 0x20000
1019 #define QLCNIC_HAS_PHYS_PORT_ID 0x40000
1020 #define QLCNIC_TSS_RSS 0x80000
1021
1022 #ifdef CONFIG_QLCNIC_VXLAN
1023 #define QLCNIC_ADD_VXLAN_PORT 0x100000
1024 #define QLCNIC_DEL_VXLAN_PORT 0x200000
1025 #endif
1026
1027 #define QLCNIC_VLAN_FILTERING 0x800000
1028
1029 #define QLCNIC_IS_MSI_FAMILY(adapter) \
1030 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
1031 #define QLCNIC_IS_TSO_CAPABLE(adapter) \
1032 ((adapter)->ahw->capabilities & QLCNIC_FW_CAPABILITY_TSO)
1033
1034 #define QLCNIC_BEACON_EANBLE 0xC
1035 #define QLCNIC_BEACON_DISABLE 0xD
1036
1037 #define QLCNIC_BEACON_ON 2
1038 #define QLCNIC_BEACON_OFF 0
1039
1040 #define QLCNIC_MSIX_TBL_SPACE 8192
1041 #define QLCNIC_PCI_REG_MSIX_TBL 0x44
1042 #define QLCNIC_MSIX_TBL_PGSIZE 4096
1043
1044 #define QLCNIC_ADAPTER_UP_MAGIC 777
1045
1046 #define __QLCNIC_FW_ATTACHED 0
1047 #define __QLCNIC_DEV_UP 1
1048 #define __QLCNIC_RESETTING 2
1049 #define __QLCNIC_START_FW 4
1050 #define __QLCNIC_AER 5
1051 #define __QLCNIC_DIAG_RES_ALLOC 6
1052 #define __QLCNIC_LED_ENABLE 7
1053 #define __QLCNIC_ELB_INPROGRESS 8
1054 #define __QLCNIC_MULTI_TX_UNIQUE 9
1055 #define __QLCNIC_SRIOV_ENABLE 10
1056 #define __QLCNIC_SRIOV_CAPABLE 11
1057 #define __QLCNIC_MBX_POLL_ENABLE 12
1058 #define __QLCNIC_DIAG_MODE 13
1059 #define __QLCNIC_MAINTENANCE_MODE 16
1060
1061 #define QLCNIC_INTERRUPT_TEST 1
1062 #define QLCNIC_LOOPBACK_TEST 2
1063 #define QLCNIC_LED_TEST 3
1064
1065 #define QLCNIC_FILTER_AGE 80
1066 #define QLCNIC_READD_AGE 20
1067 #define QLCNIC_LB_MAX_FILTERS 64
1068 #define QLCNIC_LB_BUCKET_SIZE 32
1069 #define QLCNIC_ILB_MAX_RCV_LOOP 10
1070
1071 struct qlcnic_filter {
1072 struct hlist_node fnode;
1073 u8 faddr[ETH_ALEN];
1074 u16 vlan_id;
1075 unsigned long ftime;
1076 };
1077
1078 struct qlcnic_filter_hash {
1079 struct hlist_head *fhead;
1080 u8 fnum;
1081 u16 fmax;
1082 u16 fbucket_size;
1083 };
1084
1085 /* Mailbox specific data structures */
1086 struct qlcnic_mailbox {
1087 struct workqueue_struct *work_q;
1088 struct qlcnic_adapter *adapter;
1089 struct qlcnic_mbx_ops *ops;
1090 struct work_struct work;
1091 struct completion completion;
1092 struct list_head cmd_q;
1093 unsigned long status;
1094 spinlock_t queue_lock; /* Mailbox queue lock */
1095 spinlock_t aen_lock; /* Mailbox response/AEN lock */
1096 u32 rsp_status;
1097 u32 num_cmds;
1098 };
1099
1100 struct qlcnic_adapter {
1101 struct qlcnic_hardware_context *ahw;
1102 struct qlcnic_recv_context *recv_ctx;
1103 struct qlcnic_host_tx_ring *tx_ring;
1104 struct net_device *netdev;
1105 struct pci_dev *pdev;
1106
1107 unsigned long state;
1108 u32 flags;
1109
1110 u16 num_txd;
1111 u16 num_rxd;
1112 u16 num_jumbo_rxd;
1113 u16 max_rxd;
1114 u16 max_jumbo_rxd;
1115
1116 u8 max_rds_rings;
1117
1118 u8 max_sds_rings; /* max sds rings supported by adapter */
1119 u8 max_tx_rings; /* max tx rings supported by adapter */
1120
1121 u8 drv_tx_rings; /* max tx rings supported by driver */
1122 u8 drv_sds_rings; /* max sds rings supported by driver */
1123
1124 u8 drv_tss_rings; /* tss ring input */
1125 u8 drv_rss_rings; /* rss ring input */
1126
1127 u8 rx_csum;
1128 u8 portnum;
1129
1130 u8 fw_wait_cnt;
1131 u8 fw_fail_cnt;
1132 u8 tx_timeo_cnt;
1133 u8 need_fw_reset;
1134 u8 reset_ctx_cnt;
1135
1136 u16 is_up;
1137 u16 rx_pvid;
1138 u16 tx_pvid;
1139
1140 u32 irq;
1141 u32 heartbeat;
1142
1143 u8 dev_state;
1144 u8 reset_ack_timeo;
1145 u8 dev_init_timeo;
1146
1147 u8 mac_addr[ETH_ALEN];
1148
1149 u64 dev_rst_time;
1150 bool drv_mac_learn;
1151 bool fdb_mac_learn;
1152 bool rx_mac_learn;
1153 unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)];
1154 u8 flash_mfg_id;
1155 struct qlcnic_npar_info *npars;
1156 struct qlcnic_eswitch *eswitch;
1157 struct qlcnic_nic_template *nic_ops;
1158
1159 struct qlcnic_adapter_stats stats;
1160 struct list_head mac_list;
1161
1162 void __iomem *tgt_mask_reg;
1163 void __iomem *tgt_status_reg;
1164 void __iomem *crb_int_state_reg;
1165 void __iomem *isr_int_vec;
1166
1167 struct msix_entry *msix_entries;
1168 struct workqueue_struct *qlcnic_wq;
1169 struct delayed_work fw_work;
1170 struct delayed_work idc_aen_work;
1171 struct delayed_work mbx_poll_work;
1172 struct qlcnic_dcb *dcb;
1173
1174 struct qlcnic_filter_hash fhash;
1175 struct qlcnic_filter_hash rx_fhash;
1176 struct list_head vf_mc_list;
1177
1178 spinlock_t mac_learn_lock;
1179 /* spinlock for catching rcv filters for eswitch traffic */
1180 spinlock_t rx_mac_learn_lock;
1181 u32 file_prd_off; /*File fw product offset*/
1182 u32 fw_version;
1183 u32 offload_flags;
1184 const struct firmware *fw;
1185 };
1186
1187 struct qlcnic_info_le {
1188 __le16 pci_func;
1189 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */
1190 __le16 phys_port;
1191 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */
1192
1193 __le32 capabilities;
1194 u8 max_mac_filters;
1195 u8 reserved1;
1196 __le16 max_mtu;
1197
1198 __le16 max_tx_ques;
1199 __le16 max_rx_ques;
1200 __le16 min_tx_bw;
1201 __le16 max_tx_bw;
1202 __le32 op_type;
1203 __le16 max_bw_reg_offset;
1204 __le16 max_linkspeed_reg_offset;
1205 __le32 capability1;
1206 __le32 capability2;
1207 __le32 capability3;
1208 __le16 max_tx_mac_filters;
1209 __le16 max_rx_mcast_mac_filters;
1210 __le16 max_rx_ucast_mac_filters;
1211 __le16 max_rx_ip_addr;
1212 __le16 max_rx_lro_flow;
1213 __le16 max_rx_status_rings;
1214 __le16 max_rx_buf_rings;
1215 __le16 max_tx_vlan_keys;
1216 u8 total_pf;
1217 u8 total_rss_engines;
1218 __le16 max_vports;
1219 __le16 linkstate_reg_offset;
1220 __le16 bit_offsets;
1221 __le16 max_local_ipv6_addrs;
1222 __le16 max_remote_ipv6_addrs;
1223 u8 reserved2[56];
1224 } __packed;
1225
1226 struct qlcnic_info {
1227 u16 pci_func;
1228 u16 op_mode;
1229 u16 phys_port;
1230 u16 switch_mode;
1231 u32 capabilities;
1232 u8 max_mac_filters;
1233 u16 max_mtu;
1234 u16 max_tx_ques;
1235 u16 max_rx_ques;
1236 u16 min_tx_bw;
1237 u16 max_tx_bw;
1238 u32 op_type;
1239 u16 max_bw_reg_offset;
1240 u16 max_linkspeed_reg_offset;
1241 u32 capability1;
1242 u32 capability2;
1243 u32 capability3;
1244 u16 max_tx_mac_filters;
1245 u16 max_rx_mcast_mac_filters;
1246 u16 max_rx_ucast_mac_filters;
1247 u16 max_rx_ip_addr;
1248 u16 max_rx_lro_flow;
1249 u16 max_rx_status_rings;
1250 u16 max_rx_buf_rings;
1251 u16 max_tx_vlan_keys;
1252 u8 total_pf;
1253 u8 total_rss_engines;
1254 u16 max_vports;
1255 u16 linkstate_reg_offset;
1256 u16 bit_offsets;
1257 u16 max_local_ipv6_addrs;
1258 u16 max_remote_ipv6_addrs;
1259 };
1260
1261 struct qlcnic_pci_info_le {
1262 __le16 id; /* pci function id */
1263 __le16 active; /* 1 = Enabled */
1264 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */
1265 __le16 default_port; /* default port number */
1266
1267 __le16 tx_min_bw; /* Multiple of 100mbpc */
1268 __le16 tx_max_bw;
1269 __le16 reserved1[2];
1270
1271 u8 mac[ETH_ALEN];
1272 __le16 func_count;
1273 u8 reserved2[104];
1274
1275 } __packed;
1276
1277 struct qlcnic_pci_info {
1278 u16 id;
1279 u16 active;
1280 u16 type;
1281 u16 default_port;
1282 u16 tx_min_bw;
1283 u16 tx_max_bw;
1284 u8 mac[ETH_ALEN];
1285 u16 func_count;
1286 };
1287
1288 struct qlcnic_npar_info {
1289 bool eswitch_status;
1290 u16 pvid;
1291 u16 min_bw;
1292 u16 max_bw;
1293 u8 phy_port;
1294 u8 type;
1295 u8 active;
1296 u8 enable_pm;
1297 u8 dest_npar;
1298 u8 discard_tagged;
1299 u8 mac_override;
1300 u8 mac_anti_spoof;
1301 u8 promisc_mode;
1302 u8 offload_flags;
1303 u8 pci_func;
1304 u8 mac[ETH_ALEN];
1305 };
1306
1307 struct qlcnic_eswitch {
1308 u8 port;
1309 u8 active_vports;
1310 u8 active_vlans;
1311 u8 active_ucast_filters;
1312 u8 max_ucast_filters;
1313 u8 max_active_vlans;
1314
1315 u32 flags;
1316 #define QLCNIC_SWITCH_ENABLE BIT_1
1317 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2
1318 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3
1319 #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4
1320 };
1321
1322
1323 /* Return codes for Error handling */
1324 #define QL_STATUS_INVALID_PARAM -1
1325
1326 #define MAX_BW 100 /* % of link speed */
1327 #define MIN_BW 1 /* % of link speed */
1328 #define MAX_VLAN_ID 4095
1329 #define MIN_VLAN_ID 2
1330 #define DEFAULT_MAC_LEARN 1
1331
1332 #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID)
1333 #define IS_VALID_BW(bw) (bw <= MAX_BW)
1334
1335 struct qlcnic_pci_func_cfg {
1336 u16 func_type;
1337 u16 min_bw;
1338 u16 max_bw;
1339 u16 port_num;
1340 u8 pci_func;
1341 u8 func_state;
1342 u8 def_mac_addr[ETH_ALEN];
1343 };
1344
1345 struct qlcnic_npar_func_cfg {
1346 u32 fw_capab;
1347 u16 port_num;
1348 u16 min_bw;
1349 u16 max_bw;
1350 u16 max_tx_queues;
1351 u16 max_rx_queues;
1352 u8 pci_func;
1353 u8 op_mode;
1354 };
1355
1356 struct qlcnic_pm_func_cfg {
1357 u8 pci_func;
1358 u8 action;
1359 u8 dest_npar;
1360 u8 reserved[5];
1361 };
1362
1363 struct qlcnic_esw_func_cfg {
1364 u16 vlan_id;
1365 u8 op_mode;
1366 u8 op_type;
1367 u8 pci_func;
1368 u8 host_vlan_tag;
1369 u8 promisc_mode;
1370 u8 discard_tagged;
1371 u8 mac_override;
1372 u8 mac_anti_spoof;
1373 u8 offload_flags;
1374 u8 reserved[5];
1375 };
1376
1377 #define QLCNIC_STATS_VERSION 1
1378 #define QLCNIC_STATS_PORT 1
1379 #define QLCNIC_STATS_ESWITCH 2
1380 #define QLCNIC_QUERY_RX_COUNTER 0
1381 #define QLCNIC_QUERY_TX_COUNTER 1
1382 #define QLCNIC_STATS_NOT_AVAIL 0xffffffffffffffffULL
1383 #define QLCNIC_FILL_STATS(VAL1) \
1384 (((VAL1) == QLCNIC_STATS_NOT_AVAIL) ? 0 : VAL1)
1385 #define QLCNIC_MAC_STATS 1
1386 #define QLCNIC_ESW_STATS 2
1387
1388 #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\
1389 do { \
1390 if (((VAL1) == QLCNIC_STATS_NOT_AVAIL) && \
1391 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \
1392 (VAL1) = (VAL2); \
1393 else if (((VAL1) != QLCNIC_STATS_NOT_AVAIL) && \
1394 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \
1395 (VAL1) += (VAL2); \
1396 } while (0)
1397
1398 struct qlcnic_mac_statistics_le {
1399 __le64 mac_tx_frames;
1400 __le64 mac_tx_bytes;
1401 __le64 mac_tx_mcast_pkts;
1402 __le64 mac_tx_bcast_pkts;
1403 __le64 mac_tx_pause_cnt;
1404 __le64 mac_tx_ctrl_pkt;
1405 __le64 mac_tx_lt_64b_pkts;
1406 __le64 mac_tx_lt_127b_pkts;
1407 __le64 mac_tx_lt_255b_pkts;
1408 __le64 mac_tx_lt_511b_pkts;
1409 __le64 mac_tx_lt_1023b_pkts;
1410 __le64 mac_tx_lt_1518b_pkts;
1411 __le64 mac_tx_gt_1518b_pkts;
1412 __le64 rsvd1[3];
1413
1414 __le64 mac_rx_frames;
1415 __le64 mac_rx_bytes;
1416 __le64 mac_rx_mcast_pkts;
1417 __le64 mac_rx_bcast_pkts;
1418 __le64 mac_rx_pause_cnt;
1419 __le64 mac_rx_ctrl_pkt;
1420 __le64 mac_rx_lt_64b_pkts;
1421 __le64 mac_rx_lt_127b_pkts;
1422 __le64 mac_rx_lt_255b_pkts;
1423 __le64 mac_rx_lt_511b_pkts;
1424 __le64 mac_rx_lt_1023b_pkts;
1425 __le64 mac_rx_lt_1518b_pkts;
1426 __le64 mac_rx_gt_1518b_pkts;
1427 __le64 rsvd2[3];
1428
1429 __le64 mac_rx_length_error;
1430 __le64 mac_rx_length_small;
1431 __le64 mac_rx_length_large;
1432 __le64 mac_rx_jabber;
1433 __le64 mac_rx_dropped;
1434 __le64 mac_rx_crc_error;
1435 __le64 mac_align_error;
1436 } __packed;
1437
1438 struct qlcnic_mac_statistics {
1439 u64 mac_tx_frames;
1440 u64 mac_tx_bytes;
1441 u64 mac_tx_mcast_pkts;
1442 u64 mac_tx_bcast_pkts;
1443 u64 mac_tx_pause_cnt;
1444 u64 mac_tx_ctrl_pkt;
1445 u64 mac_tx_lt_64b_pkts;
1446 u64 mac_tx_lt_127b_pkts;
1447 u64 mac_tx_lt_255b_pkts;
1448 u64 mac_tx_lt_511b_pkts;
1449 u64 mac_tx_lt_1023b_pkts;
1450 u64 mac_tx_lt_1518b_pkts;
1451 u64 mac_tx_gt_1518b_pkts;
1452 u64 rsvd1[3];
1453 u64 mac_rx_frames;
1454 u64 mac_rx_bytes;
1455 u64 mac_rx_mcast_pkts;
1456 u64 mac_rx_bcast_pkts;
1457 u64 mac_rx_pause_cnt;
1458 u64 mac_rx_ctrl_pkt;
1459 u64 mac_rx_lt_64b_pkts;
1460 u64 mac_rx_lt_127b_pkts;
1461 u64 mac_rx_lt_255b_pkts;
1462 u64 mac_rx_lt_511b_pkts;
1463 u64 mac_rx_lt_1023b_pkts;
1464 u64 mac_rx_lt_1518b_pkts;
1465 u64 mac_rx_gt_1518b_pkts;
1466 u64 rsvd2[3];
1467 u64 mac_rx_length_error;
1468 u64 mac_rx_length_small;
1469 u64 mac_rx_length_large;
1470 u64 mac_rx_jabber;
1471 u64 mac_rx_dropped;
1472 u64 mac_rx_crc_error;
1473 u64 mac_align_error;
1474 };
1475
1476 struct qlcnic_esw_stats_le {
1477 __le16 context_id;
1478 __le16 version;
1479 __le16 size;
1480 __le16 unused;
1481 __le64 unicast_frames;
1482 __le64 multicast_frames;
1483 __le64 broadcast_frames;
1484 __le64 dropped_frames;
1485 __le64 errors;
1486 __le64 local_frames;
1487 __le64 numbytes;
1488 __le64 rsvd[3];
1489 } __packed;
1490
1491 struct __qlcnic_esw_statistics {
1492 u16 context_id;
1493 u16 version;
1494 u16 size;
1495 u16 unused;
1496 u64 unicast_frames;
1497 u64 multicast_frames;
1498 u64 broadcast_frames;
1499 u64 dropped_frames;
1500 u64 errors;
1501 u64 local_frames;
1502 u64 numbytes;
1503 u64 rsvd[3];
1504 };
1505
1506 struct qlcnic_esw_statistics {
1507 struct __qlcnic_esw_statistics rx;
1508 struct __qlcnic_esw_statistics tx;
1509 };
1510
1511 #define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed
1512 #define QLCNIC_ENABLE_FW_DUMP 0xaddfeed
1513 #define QLCNIC_DISABLE_FW_DUMP 0xbadfeed
1514 #define QLCNIC_FORCE_FW_RESET 0xdeaddead
1515 #define QLCNIC_SET_QUIESCENT 0xadd00010
1516 #define QLCNIC_RESET_QUIESCENT 0xadd00020
1517
1518 struct _cdrp_cmd {
1519 u32 num;
1520 u32 *arg;
1521 };
1522
1523 struct qlcnic_cmd_args {
1524 struct completion completion;
1525 struct list_head list;
1526 struct _cdrp_cmd req;
1527 struct _cdrp_cmd rsp;
1528 atomic_t rsp_status;
1529 int pay_size;
1530 u32 rsp_opcode;
1531 u32 total_cmds;
1532 u32 op_type;
1533 u32 type;
1534 u32 cmd_op;
1535 u32 *hdr; /* Back channel message header */
1536 u32 *pay; /* Back channel message payload */
1537 u8 func_num;
1538 };
1539
1540 int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter);
1541 int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config);
1542 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data);
1543 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data);
1544
1545 #define ADDR_IN_RANGE(addr, low, high) \
1546 (((addr) < (high)) && ((addr) >= (low)))
1547
1548 #define QLCRD32(adapter, off, err) \
1549 (adapter->ahw->hw_ops->read_reg)(adapter, off, err)
1550
1551 #define QLCWR32(adapter, off, val) \
1552 adapter->ahw->hw_ops->write_reg(adapter, off, val)
1553
1554 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32);
1555 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
1556
1557 #define qlcnic_rom_lock(a) \
1558 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID)
1559 #define qlcnic_rom_unlock(a) \
1560 qlcnic_pcie_sem_unlock((a), 2)
1561 #define qlcnic_phy_lock(a) \
1562 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID)
1563 #define qlcnic_phy_unlock(a) \
1564 qlcnic_pcie_sem_unlock((a), 3)
1565 #define qlcnic_sw_lock(a) \
1566 qlcnic_pcie_sem_lock((a), 6, 0)
1567 #define qlcnic_sw_unlock(a) \
1568 qlcnic_pcie_sem_unlock((a), 6)
1569 #define crb_win_lock(a) \
1570 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID)
1571 #define crb_win_unlock(a) \
1572 qlcnic_pcie_sem_unlock((a), 7)
1573
1574 #define __QLCNIC_MAX_LED_RATE 0xf
1575 #define __QLCNIC_MAX_LED_STATE 0x2
1576
1577 #define MAX_CTL_CHECK 1000
1578
1579 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter);
1580 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter);
1581 int qlcnic_dump_fw(struct qlcnic_adapter *);
1582 int qlcnic_enable_fw_dump_state(struct qlcnic_adapter *);
1583 bool qlcnic_check_fw_dump_state(struct qlcnic_adapter *);
1584
1585 /* Functions from qlcnic_init.c */
1586 void qlcnic_schedule_work(struct qlcnic_adapter *, work_func_t, int);
1587 int qlcnic_load_firmware(struct qlcnic_adapter *adapter);
1588 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter);
1589 void qlcnic_request_firmware(struct qlcnic_adapter *adapter);
1590 void qlcnic_release_firmware(struct qlcnic_adapter *adapter);
1591 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter);
1592 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter);
1593 int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter);
1594
1595 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp);
1596 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
1597 u8 *bytes, size_t size);
1598 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter);
1599 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter);
1600
1601 void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *, u32);
1602
1603 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter);
1604 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter);
1605
1606 int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter);
1607 void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter);
1608
1609 void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter);
1610 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter);
1611 void qlcnic_release_tx_buffers(struct qlcnic_adapter *,
1612 struct qlcnic_host_tx_ring *);
1613
1614 int qlcnic_check_fw_status(struct qlcnic_adapter *adapter);
1615 void qlcnic_watchdog_task(struct work_struct *work);
1616 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter,
1617 struct qlcnic_host_rds_ring *rds_ring, u8 ring_id);
1618 void qlcnic_set_multi(struct net_device *netdev);
1619 int qlcnic_nic_add_mac(struct qlcnic_adapter *, const u8 *, u16);
1620 int qlcnic_nic_del_mac(struct qlcnic_adapter *, const u8 *);
1621 void qlcnic_82xx_free_mac_list(struct qlcnic_adapter *adapter);
1622 int qlcnic_82xx_read_phys_port_id(struct qlcnic_adapter *);
1623
1624 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu);
1625 int qlcnic_fw_cmd_set_drv_version(struct qlcnic_adapter *, u32);
1626 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu);
1627 netdev_features_t qlcnic_fix_features(struct net_device *netdev,
1628 netdev_features_t features);
1629 int qlcnic_set_features(struct net_device *netdev, netdev_features_t features);
1630 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable);
1631 void qlcnic_update_cmd_producer(struct qlcnic_host_tx_ring *);
1632
1633 /* Functions from qlcnic_ethtool.c */
1634 int qlcnic_check_loopback_buff(unsigned char *, u8 []);
1635 int qlcnic_do_lb_test(struct qlcnic_adapter *, u8);
1636
1637 /* Functions from qlcnic_main.c */
1638 int qlcnic_reset_context(struct qlcnic_adapter *);
1639 void qlcnic_diag_free_res(struct net_device *netdev, int);
1640 int qlcnic_diag_alloc_res(struct net_device *netdev, int);
1641 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *, struct net_device *);
1642 void qlcnic_set_tx_ring_count(struct qlcnic_adapter *, u8);
1643 void qlcnic_set_sds_ring_count(struct qlcnic_adapter *, u8);
1644 int qlcnic_setup_rings(struct qlcnic_adapter *);
1645 int qlcnic_validate_rings(struct qlcnic_adapter *, __u32, int);
1646 void qlcnic_alloc_lb_filters_mem(struct qlcnic_adapter *adapter);
1647 int qlcnic_enable_msix(struct qlcnic_adapter *, u32);
1648 void qlcnic_set_drv_version(struct qlcnic_adapter *);
1649
1650 /* eSwitch management functions */
1651 int qlcnic_config_switch_port(struct qlcnic_adapter *,
1652 struct qlcnic_esw_func_cfg *);
1653
1654 int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *,
1655 struct qlcnic_esw_func_cfg *);
1656 int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8);
1657 int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8,
1658 struct __qlcnic_esw_statistics *);
1659 int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8,
1660 struct __qlcnic_esw_statistics *);
1661 int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8);
1662 int qlcnic_get_mac_stats(struct qlcnic_adapter *, struct qlcnic_mac_statistics *);
1663
1664 void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd);
1665
1666 int qlcnic_alloc_sds_rings(struct qlcnic_recv_context *, int);
1667 void qlcnic_free_sds_rings(struct qlcnic_recv_context *);
1668 void qlcnic_advert_link_change(struct qlcnic_adapter *, int);
1669 void qlcnic_free_tx_rings(struct qlcnic_adapter *);
1670 int qlcnic_alloc_tx_rings(struct qlcnic_adapter *, struct net_device *);
1671 void qlcnic_dump_mbx(struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1672
1673 void qlcnic_create_sysfs_entries(struct qlcnic_adapter *adapter);
1674 void qlcnic_remove_sysfs_entries(struct qlcnic_adapter *adapter);
1675 void qlcnic_82xx_add_sysfs(struct qlcnic_adapter *adapter);
1676 void qlcnic_82xx_remove_sysfs(struct qlcnic_adapter *adapter);
1677
1678 int qlcnicvf_config_bridged_mode(struct qlcnic_adapter *, u32);
1679 int qlcnicvf_config_led(struct qlcnic_adapter *, u32, u32);
1680 void qlcnic_set_vlan_config(struct qlcnic_adapter *,
1681 struct qlcnic_esw_func_cfg *);
1682 void qlcnic_set_eswitch_port_features(struct qlcnic_adapter *,
1683 struct qlcnic_esw_func_cfg *);
1684 int qlcnic_setup_tss_rss_intr(struct qlcnic_adapter *);
1685 void qlcnic_down(struct qlcnic_adapter *, struct net_device *);
1686 int qlcnic_up(struct qlcnic_adapter *, struct net_device *);
1687 void __qlcnic_down(struct qlcnic_adapter *, struct net_device *);
1688 void qlcnic_detach(struct qlcnic_adapter *);
1689 void qlcnic_teardown_intr(struct qlcnic_adapter *);
1690 int qlcnic_attach(struct qlcnic_adapter *);
1691 int __qlcnic_up(struct qlcnic_adapter *, struct net_device *);
1692 void qlcnic_restore_indev_addr(struct net_device *, unsigned long);
1693
1694 int qlcnic_check_temp(struct qlcnic_adapter *);
1695 int qlcnic_init_pci_info(struct qlcnic_adapter *);
1696 int qlcnic_set_default_offload_settings(struct qlcnic_adapter *);
1697 int qlcnic_reset_npar_config(struct qlcnic_adapter *);
1698 int qlcnic_set_eswitch_port_config(struct qlcnic_adapter *);
1699 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter);
1700 int qlcnic_read_mac_addr(struct qlcnic_adapter *);
1701 int qlcnic_setup_netdev(struct qlcnic_adapter *, struct net_device *, int);
1702 void qlcnic_set_netdev_features(struct qlcnic_adapter *,
1703 struct qlcnic_esw_func_cfg *);
1704 void qlcnic_sriov_vf_set_multi(struct net_device *);
1705 int qlcnic_is_valid_nic_func(struct qlcnic_adapter *, u8);
1706 int qlcnic_get_pci_func_type(struct qlcnic_adapter *, u16, u16 *, u16 *,
1707 u16 *);
1708
1709 /*
1710 * QLOGIC Board information
1711 */
1712
1713 #define QLCNIC_MAX_BOARD_NAME_LEN 100
1714 struct qlcnic_board_info {
1715 unsigned short vendor;
1716 unsigned short device;
1717 unsigned short sub_vendor;
1718 unsigned short sub_device;
1719 char short_name[QLCNIC_MAX_BOARD_NAME_LEN];
1720 };
1721
qlcnic_tx_avail(struct qlcnic_host_tx_ring * tx_ring)1722 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring)
1723 {
1724 if (likely(tx_ring->producer < tx_ring->sw_consumer))
1725 return tx_ring->sw_consumer - tx_ring->producer;
1726 else
1727 return tx_ring->sw_consumer + tx_ring->num_desc -
1728 tx_ring->producer;
1729 }
1730
1731 struct qlcnic_nic_template {
1732 int (*config_bridged_mode) (struct qlcnic_adapter *, u32);
1733 int (*config_led) (struct qlcnic_adapter *, u32, u32);
1734 int (*start_firmware) (struct qlcnic_adapter *);
1735 int (*init_driver) (struct qlcnic_adapter *);
1736 void (*request_reset) (struct qlcnic_adapter *, u32);
1737 void (*cancel_idc_work) (struct qlcnic_adapter *);
1738 int (*napi_add)(struct qlcnic_adapter *, struct net_device *);
1739 void (*napi_del)(struct qlcnic_adapter *);
1740 void (*config_ipaddr)(struct qlcnic_adapter *, __be32, int);
1741 irqreturn_t (*clear_legacy_intr)(struct qlcnic_adapter *);
1742 int (*shutdown)(struct pci_dev *);
1743 int (*resume)(struct qlcnic_adapter *);
1744 };
1745
1746 struct qlcnic_mbx_ops {
1747 int (*enqueue_cmd) (struct qlcnic_adapter *,
1748 struct qlcnic_cmd_args *, unsigned long *);
1749 void (*dequeue_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1750 void (*decode_resp) (struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1751 void (*encode_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1752 void (*nofity_fw) (struct qlcnic_adapter *, u8);
1753 };
1754
1755 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *);
1756 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *);
1757 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx);
1758 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx);
1759 void qlcnic_update_stats(struct qlcnic_adapter *);
1760
1761 /* Adapter hardware abstraction */
1762 struct qlcnic_hardware_ops {
1763 void (*read_crb) (struct qlcnic_adapter *, char *, loff_t, size_t);
1764 void (*write_crb) (struct qlcnic_adapter *, char *, loff_t, size_t);
1765 int (*read_reg) (struct qlcnic_adapter *, ulong, int *);
1766 int (*write_reg) (struct qlcnic_adapter *, ulong, u32);
1767 void (*get_ocm_win) (struct qlcnic_hardware_context *);
1768 int (*get_mac_address) (struct qlcnic_adapter *, u8 *, u8);
1769 int (*setup_intr) (struct qlcnic_adapter *);
1770 int (*alloc_mbx_args)(struct qlcnic_cmd_args *,
1771 struct qlcnic_adapter *, u32);
1772 int (*mbx_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1773 void (*get_func_no) (struct qlcnic_adapter *);
1774 int (*api_lock) (struct qlcnic_adapter *);
1775 void (*api_unlock) (struct qlcnic_adapter *);
1776 void (*add_sysfs) (struct qlcnic_adapter *);
1777 void (*remove_sysfs) (struct qlcnic_adapter *);
1778 void (*process_lb_rcv_ring_diag) (struct qlcnic_host_sds_ring *);
1779 int (*create_rx_ctx) (struct qlcnic_adapter *);
1780 int (*create_tx_ctx) (struct qlcnic_adapter *,
1781 struct qlcnic_host_tx_ring *, int);
1782 void (*del_rx_ctx) (struct qlcnic_adapter *);
1783 void (*del_tx_ctx) (struct qlcnic_adapter *,
1784 struct qlcnic_host_tx_ring *);
1785 int (*setup_link_event) (struct qlcnic_adapter *, int);
1786 int (*get_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *, u8);
1787 int (*get_pci_info) (struct qlcnic_adapter *, struct qlcnic_pci_info *);
1788 int (*set_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *);
1789 int (*change_macvlan) (struct qlcnic_adapter *, u8*, u16, u8);
1790 void (*napi_enable) (struct qlcnic_adapter *);
1791 void (*napi_disable) (struct qlcnic_adapter *);
1792 int (*config_intr_coal) (struct qlcnic_adapter *,
1793 struct ethtool_coalesce *);
1794 int (*config_rss) (struct qlcnic_adapter *, int);
1795 int (*config_hw_lro) (struct qlcnic_adapter *, int);
1796 int (*config_loopback) (struct qlcnic_adapter *, u8);
1797 int (*clear_loopback) (struct qlcnic_adapter *, u8);
1798 int (*config_promisc_mode) (struct qlcnic_adapter *, u32);
1799 void (*change_l2_filter) (struct qlcnic_adapter *, u64 *, u16);
1800 int (*get_board_info) (struct qlcnic_adapter *);
1801 void (*set_mac_filter_count) (struct qlcnic_adapter *);
1802 void (*free_mac_list) (struct qlcnic_adapter *);
1803 int (*read_phys_port_id) (struct qlcnic_adapter *);
1804 pci_ers_result_t (*io_error_detected) (struct pci_dev *,
1805 pci_channel_state_t);
1806 pci_ers_result_t (*io_slot_reset) (struct pci_dev *);
1807 void (*io_resume) (struct pci_dev *);
1808 void (*get_beacon_state)(struct qlcnic_adapter *);
1809 void (*enable_sds_intr) (struct qlcnic_adapter *,
1810 struct qlcnic_host_sds_ring *);
1811 void (*disable_sds_intr) (struct qlcnic_adapter *,
1812 struct qlcnic_host_sds_ring *);
1813 void (*enable_tx_intr) (struct qlcnic_adapter *,
1814 struct qlcnic_host_tx_ring *);
1815 void (*disable_tx_intr) (struct qlcnic_adapter *,
1816 struct qlcnic_host_tx_ring *);
1817 u32 (*get_saved_state)(void *, u32);
1818 void (*set_saved_state)(void *, u32, u32);
1819 void (*cache_tmpl_hdr_values)(struct qlcnic_fw_dump *);
1820 u32 (*get_cap_size)(void *, int);
1821 void (*set_sys_info)(void *, int, u32);
1822 void (*store_cap_mask)(void *, u32);
1823 };
1824
1825 extern struct qlcnic_nic_template qlcnic_vf_ops;
1826
qlcnic_encap_tx_offload(struct qlcnic_adapter * adapter)1827 static inline bool qlcnic_encap_tx_offload(struct qlcnic_adapter *adapter)
1828 {
1829 return adapter->ahw->extra_capability[0] &
1830 QLCNIC_83XX_FW_CAPAB_ENCAP_TX_OFFLOAD;
1831 }
1832
qlcnic_encap_rx_offload(struct qlcnic_adapter * adapter)1833 static inline bool qlcnic_encap_rx_offload(struct qlcnic_adapter *adapter)
1834 {
1835 return adapter->ahw->extra_capability[0] &
1836 QLCNIC_83XX_FW_CAPAB_ENCAP_RX_OFFLOAD;
1837 }
1838
qlcnic_start_firmware(struct qlcnic_adapter * adapter)1839 static inline int qlcnic_start_firmware(struct qlcnic_adapter *adapter)
1840 {
1841 return adapter->nic_ops->start_firmware(adapter);
1842 }
1843
qlcnic_read_crb(struct qlcnic_adapter * adapter,char * buf,loff_t offset,size_t size)1844 static inline void qlcnic_read_crb(struct qlcnic_adapter *adapter, char *buf,
1845 loff_t offset, size_t size)
1846 {
1847 adapter->ahw->hw_ops->read_crb(adapter, buf, offset, size);
1848 }
1849
qlcnic_write_crb(struct qlcnic_adapter * adapter,char * buf,loff_t offset,size_t size)1850 static inline void qlcnic_write_crb(struct qlcnic_adapter *adapter, char *buf,
1851 loff_t offset, size_t size)
1852 {
1853 adapter->ahw->hw_ops->write_crb(adapter, buf, offset, size);
1854 }
1855
qlcnic_hw_write_wx_2M(struct qlcnic_adapter * adapter,ulong off,u32 data)1856 static inline int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter,
1857 ulong off, u32 data)
1858 {
1859 return adapter->ahw->hw_ops->write_reg(adapter, off, data);
1860 }
1861
qlcnic_get_mac_address(struct qlcnic_adapter * adapter,u8 * mac,u8 function)1862 static inline int qlcnic_get_mac_address(struct qlcnic_adapter *adapter,
1863 u8 *mac, u8 function)
1864 {
1865 return adapter->ahw->hw_ops->get_mac_address(adapter, mac, function);
1866 }
1867
qlcnic_setup_intr(struct qlcnic_adapter * adapter)1868 static inline int qlcnic_setup_intr(struct qlcnic_adapter *adapter)
1869 {
1870 return adapter->ahw->hw_ops->setup_intr(adapter);
1871 }
1872
qlcnic_alloc_mbx_args(struct qlcnic_cmd_args * mbx,struct qlcnic_adapter * adapter,u32 arg)1873 static inline int qlcnic_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
1874 struct qlcnic_adapter *adapter, u32 arg)
1875 {
1876 return adapter->ahw->hw_ops->alloc_mbx_args(mbx, adapter, arg);
1877 }
1878
qlcnic_issue_cmd(struct qlcnic_adapter * adapter,struct qlcnic_cmd_args * cmd)1879 static inline int qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
1880 struct qlcnic_cmd_args *cmd)
1881 {
1882 if (adapter->ahw->hw_ops->mbx_cmd)
1883 return adapter->ahw->hw_ops->mbx_cmd(adapter, cmd);
1884
1885 return -EIO;
1886 }
1887
qlcnic_get_func_no(struct qlcnic_adapter * adapter)1888 static inline void qlcnic_get_func_no(struct qlcnic_adapter *adapter)
1889 {
1890 adapter->ahw->hw_ops->get_func_no(adapter);
1891 }
1892
qlcnic_api_lock(struct qlcnic_adapter * adapter)1893 static inline int qlcnic_api_lock(struct qlcnic_adapter *adapter)
1894 {
1895 return adapter->ahw->hw_ops->api_lock(adapter);
1896 }
1897
qlcnic_api_unlock(struct qlcnic_adapter * adapter)1898 static inline void qlcnic_api_unlock(struct qlcnic_adapter *adapter)
1899 {
1900 adapter->ahw->hw_ops->api_unlock(adapter);
1901 }
1902
qlcnic_add_sysfs(struct qlcnic_adapter * adapter)1903 static inline void qlcnic_add_sysfs(struct qlcnic_adapter *adapter)
1904 {
1905 if (adapter->ahw->hw_ops->add_sysfs)
1906 adapter->ahw->hw_ops->add_sysfs(adapter);
1907 }
1908
qlcnic_remove_sysfs(struct qlcnic_adapter * adapter)1909 static inline void qlcnic_remove_sysfs(struct qlcnic_adapter *adapter)
1910 {
1911 if (adapter->ahw->hw_ops->remove_sysfs)
1912 adapter->ahw->hw_ops->remove_sysfs(adapter);
1913 }
1914
1915 static inline void
qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring * sds_ring)1916 qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring)
1917 {
1918 sds_ring->adapter->ahw->hw_ops->process_lb_rcv_ring_diag(sds_ring);
1919 }
1920
qlcnic_fw_cmd_create_rx_ctx(struct qlcnic_adapter * adapter)1921 static inline int qlcnic_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter)
1922 {
1923 return adapter->ahw->hw_ops->create_rx_ctx(adapter);
1924 }
1925
qlcnic_fw_cmd_create_tx_ctx(struct qlcnic_adapter * adapter,struct qlcnic_host_tx_ring * ptr,int ring)1926 static inline int qlcnic_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter,
1927 struct qlcnic_host_tx_ring *ptr,
1928 int ring)
1929 {
1930 return adapter->ahw->hw_ops->create_tx_ctx(adapter, ptr, ring);
1931 }
1932
qlcnic_fw_cmd_del_rx_ctx(struct qlcnic_adapter * adapter)1933 static inline void qlcnic_fw_cmd_del_rx_ctx(struct qlcnic_adapter *adapter)
1934 {
1935 return adapter->ahw->hw_ops->del_rx_ctx(adapter);
1936 }
1937
qlcnic_fw_cmd_del_tx_ctx(struct qlcnic_adapter * adapter,struct qlcnic_host_tx_ring * ptr)1938 static inline void qlcnic_fw_cmd_del_tx_ctx(struct qlcnic_adapter *adapter,
1939 struct qlcnic_host_tx_ring *ptr)
1940 {
1941 return adapter->ahw->hw_ops->del_tx_ctx(adapter, ptr);
1942 }
1943
qlcnic_linkevent_request(struct qlcnic_adapter * adapter,int enable)1944 static inline int qlcnic_linkevent_request(struct qlcnic_adapter *adapter,
1945 int enable)
1946 {
1947 return adapter->ahw->hw_ops->setup_link_event(adapter, enable);
1948 }
1949
qlcnic_get_nic_info(struct qlcnic_adapter * adapter,struct qlcnic_info * info,u8 id)1950 static inline int qlcnic_get_nic_info(struct qlcnic_adapter *adapter,
1951 struct qlcnic_info *info, u8 id)
1952 {
1953 return adapter->ahw->hw_ops->get_nic_info(adapter, info, id);
1954 }
1955
qlcnic_get_pci_info(struct qlcnic_adapter * adapter,struct qlcnic_pci_info * info)1956 static inline int qlcnic_get_pci_info(struct qlcnic_adapter *adapter,
1957 struct qlcnic_pci_info *info)
1958 {
1959 return adapter->ahw->hw_ops->get_pci_info(adapter, info);
1960 }
1961
qlcnic_set_nic_info(struct qlcnic_adapter * adapter,struct qlcnic_info * info)1962 static inline int qlcnic_set_nic_info(struct qlcnic_adapter *adapter,
1963 struct qlcnic_info *info)
1964 {
1965 return adapter->ahw->hw_ops->set_nic_info(adapter, info);
1966 }
1967
qlcnic_sre_macaddr_change(struct qlcnic_adapter * adapter,u8 * addr,u16 id,u8 cmd)1968 static inline int qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter,
1969 u8 *addr, u16 id, u8 cmd)
1970 {
1971 return adapter->ahw->hw_ops->change_macvlan(adapter, addr, id, cmd);
1972 }
1973
qlcnic_napi_add(struct qlcnic_adapter * adapter,struct net_device * netdev)1974 static inline int qlcnic_napi_add(struct qlcnic_adapter *adapter,
1975 struct net_device *netdev)
1976 {
1977 return adapter->nic_ops->napi_add(adapter, netdev);
1978 }
1979
qlcnic_napi_del(struct qlcnic_adapter * adapter)1980 static inline void qlcnic_napi_del(struct qlcnic_adapter *adapter)
1981 {
1982 adapter->nic_ops->napi_del(adapter);
1983 }
1984
qlcnic_napi_enable(struct qlcnic_adapter * adapter)1985 static inline void qlcnic_napi_enable(struct qlcnic_adapter *adapter)
1986 {
1987 adapter->ahw->hw_ops->napi_enable(adapter);
1988 }
1989
__qlcnic_shutdown(struct pci_dev * pdev)1990 static inline int __qlcnic_shutdown(struct pci_dev *pdev)
1991 {
1992 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
1993
1994 return adapter->nic_ops->shutdown(pdev);
1995 }
1996
__qlcnic_resume(struct qlcnic_adapter * adapter)1997 static inline int __qlcnic_resume(struct qlcnic_adapter *adapter)
1998 {
1999 return adapter->nic_ops->resume(adapter);
2000 }
2001
qlcnic_napi_disable(struct qlcnic_adapter * adapter)2002 static inline void qlcnic_napi_disable(struct qlcnic_adapter *adapter)
2003 {
2004 adapter->ahw->hw_ops->napi_disable(adapter);
2005 }
2006
qlcnic_config_intr_coalesce(struct qlcnic_adapter * adapter,struct ethtool_coalesce * ethcoal)2007 static inline int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter,
2008 struct ethtool_coalesce *ethcoal)
2009 {
2010 return adapter->ahw->hw_ops->config_intr_coal(adapter, ethcoal);
2011 }
2012
qlcnic_config_rss(struct qlcnic_adapter * adapter,int enable)2013 static inline int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable)
2014 {
2015 return adapter->ahw->hw_ops->config_rss(adapter, enable);
2016 }
2017
qlcnic_config_hw_lro(struct qlcnic_adapter * adapter,int enable)2018 static inline int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter,
2019 int enable)
2020 {
2021 return adapter->ahw->hw_ops->config_hw_lro(adapter, enable);
2022 }
2023
qlcnic_set_lb_mode(struct qlcnic_adapter * adapter,u8 mode)2024 static inline int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
2025 {
2026 return adapter->ahw->hw_ops->config_loopback(adapter, mode);
2027 }
2028
qlcnic_clear_lb_mode(struct qlcnic_adapter * adapter,u8 mode)2029 static inline int qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
2030 {
2031 return adapter->ahw->hw_ops->clear_loopback(adapter, mode);
2032 }
2033
qlcnic_nic_set_promisc(struct qlcnic_adapter * adapter,u32 mode)2034 static inline int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter,
2035 u32 mode)
2036 {
2037 return adapter->ahw->hw_ops->config_promisc_mode(adapter, mode);
2038 }
2039
qlcnic_change_filter(struct qlcnic_adapter * adapter,u64 * addr,u16 id)2040 static inline void qlcnic_change_filter(struct qlcnic_adapter *adapter,
2041 u64 *addr, u16 id)
2042 {
2043 adapter->ahw->hw_ops->change_l2_filter(adapter, addr, id);
2044 }
2045
qlcnic_get_board_info(struct qlcnic_adapter * adapter)2046 static inline int qlcnic_get_board_info(struct qlcnic_adapter *adapter)
2047 {
2048 return adapter->ahw->hw_ops->get_board_info(adapter);
2049 }
2050
qlcnic_free_mac_list(struct qlcnic_adapter * adapter)2051 static inline void qlcnic_free_mac_list(struct qlcnic_adapter *adapter)
2052 {
2053 return adapter->ahw->hw_ops->free_mac_list(adapter);
2054 }
2055
qlcnic_set_mac_filter_count(struct qlcnic_adapter * adapter)2056 static inline void qlcnic_set_mac_filter_count(struct qlcnic_adapter *adapter)
2057 {
2058 if (adapter->ahw->hw_ops->set_mac_filter_count)
2059 adapter->ahw->hw_ops->set_mac_filter_count(adapter);
2060 }
2061
qlcnic_get_beacon_state(struct qlcnic_adapter * adapter)2062 static inline void qlcnic_get_beacon_state(struct qlcnic_adapter *adapter)
2063 {
2064 adapter->ahw->hw_ops->get_beacon_state(adapter);
2065 }
2066
qlcnic_read_phys_port_id(struct qlcnic_adapter * adapter)2067 static inline void qlcnic_read_phys_port_id(struct qlcnic_adapter *adapter)
2068 {
2069 if (adapter->ahw->hw_ops->read_phys_port_id)
2070 adapter->ahw->hw_ops->read_phys_port_id(adapter);
2071 }
2072
qlcnic_get_saved_state(struct qlcnic_adapter * adapter,void * t_hdr,u32 index)2073 static inline u32 qlcnic_get_saved_state(struct qlcnic_adapter *adapter,
2074 void *t_hdr, u32 index)
2075 {
2076 return adapter->ahw->hw_ops->get_saved_state(t_hdr, index);
2077 }
2078
qlcnic_set_saved_state(struct qlcnic_adapter * adapter,void * t_hdr,u32 index,u32 value)2079 static inline void qlcnic_set_saved_state(struct qlcnic_adapter *adapter,
2080 void *t_hdr, u32 index, u32 value)
2081 {
2082 adapter->ahw->hw_ops->set_saved_state(t_hdr, index, value);
2083 }
2084
qlcnic_cache_tmpl_hdr_values(struct qlcnic_adapter * adapter,struct qlcnic_fw_dump * fw_dump)2085 static inline void qlcnic_cache_tmpl_hdr_values(struct qlcnic_adapter *adapter,
2086 struct qlcnic_fw_dump *fw_dump)
2087 {
2088 adapter->ahw->hw_ops->cache_tmpl_hdr_values(fw_dump);
2089 }
2090
qlcnic_get_cap_size(struct qlcnic_adapter * adapter,void * tmpl_hdr,int index)2091 static inline u32 qlcnic_get_cap_size(struct qlcnic_adapter *adapter,
2092 void *tmpl_hdr, int index)
2093 {
2094 return adapter->ahw->hw_ops->get_cap_size(tmpl_hdr, index);
2095 }
2096
qlcnic_set_sys_info(struct qlcnic_adapter * adapter,void * tmpl_hdr,int idx,u32 value)2097 static inline void qlcnic_set_sys_info(struct qlcnic_adapter *adapter,
2098 void *tmpl_hdr, int idx, u32 value)
2099 {
2100 adapter->ahw->hw_ops->set_sys_info(tmpl_hdr, idx, value);
2101 }
2102
qlcnic_store_cap_mask(struct qlcnic_adapter * adapter,void * tmpl_hdr,u32 mask)2103 static inline void qlcnic_store_cap_mask(struct qlcnic_adapter *adapter,
2104 void *tmpl_hdr, u32 mask)
2105 {
2106 adapter->ahw->hw_ops->store_cap_mask(tmpl_hdr, mask);
2107 }
2108
qlcnic_dev_request_reset(struct qlcnic_adapter * adapter,u32 key)2109 static inline void qlcnic_dev_request_reset(struct qlcnic_adapter *adapter,
2110 u32 key)
2111 {
2112 if (adapter->nic_ops->request_reset)
2113 adapter->nic_ops->request_reset(adapter, key);
2114 }
2115
qlcnic_cancel_idc_work(struct qlcnic_adapter * adapter)2116 static inline void qlcnic_cancel_idc_work(struct qlcnic_adapter *adapter)
2117 {
2118 if (adapter->nic_ops->cancel_idc_work)
2119 adapter->nic_ops->cancel_idc_work(adapter);
2120 }
2121
2122 static inline irqreturn_t
qlcnic_clear_legacy_intr(struct qlcnic_adapter * adapter)2123 qlcnic_clear_legacy_intr(struct qlcnic_adapter *adapter)
2124 {
2125 return adapter->nic_ops->clear_legacy_intr(adapter);
2126 }
2127
qlcnic_config_led(struct qlcnic_adapter * adapter,u32 state,u32 rate)2128 static inline int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state,
2129 u32 rate)
2130 {
2131 return adapter->nic_ops->config_led(adapter, state, rate);
2132 }
2133
qlcnic_config_ipaddr(struct qlcnic_adapter * adapter,__be32 ip,int cmd)2134 static inline void qlcnic_config_ipaddr(struct qlcnic_adapter *adapter,
2135 __be32 ip, int cmd)
2136 {
2137 adapter->nic_ops->config_ipaddr(adapter, ip, cmd);
2138 }
2139
qlcnic_check_multi_tx(struct qlcnic_adapter * adapter)2140 static inline bool qlcnic_check_multi_tx(struct qlcnic_adapter *adapter)
2141 {
2142 return test_bit(__QLCNIC_MULTI_TX_UNIQUE, &adapter->state);
2143 }
2144
2145 static inline void
qlcnic_82xx_enable_tx_intr(struct qlcnic_adapter * adapter,struct qlcnic_host_tx_ring * tx_ring)2146 qlcnic_82xx_enable_tx_intr(struct qlcnic_adapter *adapter,
2147 struct qlcnic_host_tx_ring *tx_ring)
2148 {
2149 if (qlcnic_check_multi_tx(adapter) &&
2150 !adapter->ahw->diag_test)
2151 writel(0x0, tx_ring->crb_intr_mask);
2152 }
2153
2154 static inline void
qlcnic_82xx_disable_tx_intr(struct qlcnic_adapter * adapter,struct qlcnic_host_tx_ring * tx_ring)2155 qlcnic_82xx_disable_tx_intr(struct qlcnic_adapter *adapter,
2156 struct qlcnic_host_tx_ring *tx_ring)
2157 {
2158 if (qlcnic_check_multi_tx(adapter) &&
2159 !adapter->ahw->diag_test)
2160 writel(1, tx_ring->crb_intr_mask);
2161 }
2162
2163 static inline void
qlcnic_83xx_enable_tx_intr(struct qlcnic_adapter * adapter,struct qlcnic_host_tx_ring * tx_ring)2164 qlcnic_83xx_enable_tx_intr(struct qlcnic_adapter *adapter,
2165 struct qlcnic_host_tx_ring *tx_ring)
2166 {
2167 writel(0, tx_ring->crb_intr_mask);
2168 }
2169
2170 static inline void
qlcnic_83xx_disable_tx_intr(struct qlcnic_adapter * adapter,struct qlcnic_host_tx_ring * tx_ring)2171 qlcnic_83xx_disable_tx_intr(struct qlcnic_adapter *adapter,
2172 struct qlcnic_host_tx_ring *tx_ring)
2173 {
2174 writel(1, tx_ring->crb_intr_mask);
2175 }
2176
2177 /* Enable MSI-x and INT-x interrupts */
2178 static inline void
qlcnic_83xx_enable_sds_intr(struct qlcnic_adapter * adapter,struct qlcnic_host_sds_ring * sds_ring)2179 qlcnic_83xx_enable_sds_intr(struct qlcnic_adapter *adapter,
2180 struct qlcnic_host_sds_ring *sds_ring)
2181 {
2182 writel(0, sds_ring->crb_intr_mask);
2183 }
2184
2185 /* Disable MSI-x and INT-x interrupts */
2186 static inline void
qlcnic_83xx_disable_sds_intr(struct qlcnic_adapter * adapter,struct qlcnic_host_sds_ring * sds_ring)2187 qlcnic_83xx_disable_sds_intr(struct qlcnic_adapter *adapter,
2188 struct qlcnic_host_sds_ring *sds_ring)
2189 {
2190 writel(1, sds_ring->crb_intr_mask);
2191 }
2192
qlcnic_disable_multi_tx(struct qlcnic_adapter * adapter)2193 static inline void qlcnic_disable_multi_tx(struct qlcnic_adapter *adapter)
2194 {
2195 test_and_clear_bit(__QLCNIC_MULTI_TX_UNIQUE, &adapter->state);
2196 adapter->drv_tx_rings = QLCNIC_SINGLE_RING;
2197 }
2198
2199 /* When operating in a muti tx mode, driver needs to write 0x1
2200 * to src register, instead of 0x0 to disable receiving interrupt.
2201 */
2202 static inline void
qlcnic_82xx_disable_sds_intr(struct qlcnic_adapter * adapter,struct qlcnic_host_sds_ring * sds_ring)2203 qlcnic_82xx_disable_sds_intr(struct qlcnic_adapter *adapter,
2204 struct qlcnic_host_sds_ring *sds_ring)
2205 {
2206 if (qlcnic_check_multi_tx(adapter) &&
2207 !adapter->ahw->diag_test &&
2208 (adapter->flags & QLCNIC_MSIX_ENABLED))
2209 writel(0x1, sds_ring->crb_intr_mask);
2210 else
2211 writel(0, sds_ring->crb_intr_mask);
2212 }
2213
qlcnic_enable_sds_intr(struct qlcnic_adapter * adapter,struct qlcnic_host_sds_ring * sds_ring)2214 static inline void qlcnic_enable_sds_intr(struct qlcnic_adapter *adapter,
2215 struct qlcnic_host_sds_ring *sds_ring)
2216 {
2217 if (adapter->ahw->hw_ops->enable_sds_intr)
2218 adapter->ahw->hw_ops->enable_sds_intr(adapter, sds_ring);
2219 }
2220
2221 static inline void
qlcnic_disable_sds_intr(struct qlcnic_adapter * adapter,struct qlcnic_host_sds_ring * sds_ring)2222 qlcnic_disable_sds_intr(struct qlcnic_adapter *adapter,
2223 struct qlcnic_host_sds_ring *sds_ring)
2224 {
2225 if (adapter->ahw->hw_ops->disable_sds_intr)
2226 adapter->ahw->hw_ops->disable_sds_intr(adapter, sds_ring);
2227 }
2228
qlcnic_enable_tx_intr(struct qlcnic_adapter * adapter,struct qlcnic_host_tx_ring * tx_ring)2229 static inline void qlcnic_enable_tx_intr(struct qlcnic_adapter *adapter,
2230 struct qlcnic_host_tx_ring *tx_ring)
2231 {
2232 if (adapter->ahw->hw_ops->enable_tx_intr)
2233 adapter->ahw->hw_ops->enable_tx_intr(adapter, tx_ring);
2234 }
2235
qlcnic_disable_tx_intr(struct qlcnic_adapter * adapter,struct qlcnic_host_tx_ring * tx_ring)2236 static inline void qlcnic_disable_tx_intr(struct qlcnic_adapter *adapter,
2237 struct qlcnic_host_tx_ring *tx_ring)
2238 {
2239 if (adapter->ahw->hw_ops->disable_tx_intr)
2240 adapter->ahw->hw_ops->disable_tx_intr(adapter, tx_ring);
2241 }
2242
2243 /* When operating in a muti tx mode, driver needs to write 0x0
2244 * to src register, instead of 0x1 to enable receiving interrupts.
2245 */
2246 static inline void
qlcnic_82xx_enable_sds_intr(struct qlcnic_adapter * adapter,struct qlcnic_host_sds_ring * sds_ring)2247 qlcnic_82xx_enable_sds_intr(struct qlcnic_adapter *adapter,
2248 struct qlcnic_host_sds_ring *sds_ring)
2249 {
2250 if (qlcnic_check_multi_tx(adapter) &&
2251 !adapter->ahw->diag_test &&
2252 (adapter->flags & QLCNIC_MSIX_ENABLED))
2253 writel(0, sds_ring->crb_intr_mask);
2254 else
2255 writel(0x1, sds_ring->crb_intr_mask);
2256
2257 if (!QLCNIC_IS_MSI_FAMILY(adapter))
2258 writel(0xfbff, adapter->tgt_mask_reg);
2259 }
2260
qlcnic_get_diag_lock(struct qlcnic_adapter * adapter)2261 static inline int qlcnic_get_diag_lock(struct qlcnic_adapter *adapter)
2262 {
2263 return test_and_set_bit(__QLCNIC_DIAG_MODE, &adapter->state);
2264 }
2265
qlcnic_release_diag_lock(struct qlcnic_adapter * adapter)2266 static inline void qlcnic_release_diag_lock(struct qlcnic_adapter *adapter)
2267 {
2268 clear_bit(__QLCNIC_DIAG_MODE, &adapter->state);
2269 }
2270
qlcnic_check_diag_status(struct qlcnic_adapter * adapter)2271 static inline int qlcnic_check_diag_status(struct qlcnic_adapter *adapter)
2272 {
2273 return test_bit(__QLCNIC_DIAG_MODE, &adapter->state);
2274 }
2275
2276 extern const struct ethtool_ops qlcnic_sriov_vf_ethtool_ops;
2277 extern const struct ethtool_ops qlcnic_ethtool_ops;
2278 extern const struct ethtool_ops qlcnic_ethtool_failed_ops;
2279
2280 #define QLCDB(adapter, lvl, _fmt, _args...) do { \
2281 if (NETIF_MSG_##lvl & adapter->ahw->msg_enable) \
2282 printk(KERN_INFO "%s: %s: " _fmt, \
2283 dev_name(&adapter->pdev->dev), \
2284 __func__, ##_args); \
2285 } while (0)
2286
2287 #define PCI_DEVICE_ID_QLOGIC_QLE824X 0x8020
2288 #define PCI_DEVICE_ID_QLOGIC_QLE834X 0x8030
2289 #define PCI_DEVICE_ID_QLOGIC_QLE8830 0x8830
2290 #define PCI_DEVICE_ID_QLOGIC_VF_QLE834X 0x8430
2291 #define PCI_DEVICE_ID_QLOGIC_QLE844X 0x8040
2292 #define PCI_DEVICE_ID_QLOGIC_VF_QLE844X 0x8440
2293
qlcnic_82xx_check(struct qlcnic_adapter * adapter)2294 static inline bool qlcnic_82xx_check(struct qlcnic_adapter *adapter)
2295 {
2296 unsigned short device = adapter->pdev->device;
2297 return (device == PCI_DEVICE_ID_QLOGIC_QLE824X) ? true : false;
2298 }
2299
qlcnic_84xx_check(struct qlcnic_adapter * adapter)2300 static inline bool qlcnic_84xx_check(struct qlcnic_adapter *adapter)
2301 {
2302 unsigned short device = adapter->pdev->device;
2303
2304 return ((device == PCI_DEVICE_ID_QLOGIC_QLE844X) ||
2305 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X)) ? true : false;
2306 }
2307
qlcnic_83xx_check(struct qlcnic_adapter * adapter)2308 static inline bool qlcnic_83xx_check(struct qlcnic_adapter *adapter)
2309 {
2310 unsigned short device = adapter->pdev->device;
2311 bool status;
2312
2313 status = ((device == PCI_DEVICE_ID_QLOGIC_QLE834X) ||
2314 (device == PCI_DEVICE_ID_QLOGIC_QLE8830) ||
2315 (device == PCI_DEVICE_ID_QLOGIC_QLE844X) ||
2316 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X) ||
2317 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X)) ? true : false;
2318
2319 return status;
2320 }
2321
qlcnic_sriov_pf_check(struct qlcnic_adapter * adapter)2322 static inline bool qlcnic_sriov_pf_check(struct qlcnic_adapter *adapter)
2323 {
2324 return (adapter->ahw->op_mode == QLCNIC_SRIOV_PF_FUNC) ? true : false;
2325 }
2326
qlcnic_sriov_vf_check(struct qlcnic_adapter * adapter)2327 static inline bool qlcnic_sriov_vf_check(struct qlcnic_adapter *adapter)
2328 {
2329 unsigned short device = adapter->pdev->device;
2330 bool status;
2331
2332 status = ((device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) ||
2333 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X)) ? true : false;
2334
2335 return status;
2336 }
2337
qlcnic_83xx_pf_check(struct qlcnic_adapter * adapter)2338 static inline bool qlcnic_83xx_pf_check(struct qlcnic_adapter *adapter)
2339 {
2340 unsigned short device = adapter->pdev->device;
2341
2342 return (device == PCI_DEVICE_ID_QLOGIC_QLE834X) ? true : false;
2343 }
2344
qlcnic_83xx_vf_check(struct qlcnic_adapter * adapter)2345 static inline bool qlcnic_83xx_vf_check(struct qlcnic_adapter *adapter)
2346 {
2347 unsigned short device = adapter->pdev->device;
2348
2349 return (device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) ? true : false;
2350 }
2351
qlcnic_sriov_check(struct qlcnic_adapter * adapter)2352 static inline bool qlcnic_sriov_check(struct qlcnic_adapter *adapter)
2353 {
2354 bool status;
2355
2356 status = (qlcnic_sriov_pf_check(adapter) ||
2357 qlcnic_sriov_vf_check(adapter)) ? true : false;
2358
2359 return status;
2360 }
2361
qlcnic_get_vnic_func_count(struct qlcnic_adapter * adapter)2362 static inline u32 qlcnic_get_vnic_func_count(struct qlcnic_adapter *adapter)
2363 {
2364 if (qlcnic_84xx_check(adapter))
2365 return QLC_84XX_VNIC_COUNT;
2366 else
2367 return QLC_DEFAULT_VNIC_COUNT;
2368 }
2369
qlcnic_swap32_buffer(u32 * buffer,int count)2370 static inline void qlcnic_swap32_buffer(u32 *buffer, int count)
2371 {
2372 #if defined(__BIG_ENDIAN)
2373 u32 *tmp = buffer;
2374 int i;
2375
2376 for (i = 0; i < count; i++) {
2377 *tmp = swab32(*tmp);
2378 tmp++;
2379 }
2380 #endif
2381 }
2382
2383 #ifdef CONFIG_QLCNIC_HWMON
2384 void qlcnic_register_hwmon_dev(struct qlcnic_adapter *);
2385 void qlcnic_unregister_hwmon_dev(struct qlcnic_adapter *);
2386 #else
qlcnic_register_hwmon_dev(struct qlcnic_adapter * adapter)2387 static inline void qlcnic_register_hwmon_dev(struct qlcnic_adapter *adapter)
2388 {
2389 return;
2390 }
qlcnic_unregister_hwmon_dev(struct qlcnic_adapter * adapter)2391 static inline void qlcnic_unregister_hwmon_dev(struct qlcnic_adapter *adapter)
2392 {
2393 return;
2394 }
2395 #endif
2396 #endif /* __QLCNIC_H_ */
2397