1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
23 * USA
24 *
25 * The full GNU General Public License is included in this distribution
26 * in the file called COPYING.
27 *
28 * Contact Information:
29 * Intel Linux Wireless <ilw@linux.intel.com>
30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 *
32 * BSD LICENSE
33 *
34 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
35 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
36 * All rights reserved.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 *
42 * * Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * * Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in
46 * the documentation and/or other materials provided with the
47 * distribution.
48 * * Neither the name Intel Corporation nor the names of its
49 * contributors may be used to endorse or promote products derived
50 * from this software without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *****************************************************************************/
64
65 #ifndef __iwl_prph_h__
66 #define __iwl_prph_h__
67
68 /*
69 * Registers in this file are internal, not PCI bus memory mapped.
70 * Driver accesses these via HBUS_TARG_PRPH_* registers.
71 */
72 #define PRPH_BASE (0x00000)
73 #define PRPH_END (0xFFFFF)
74
75 /* APMG (power management) constants */
76 #define APMG_BASE (PRPH_BASE + 0x3000)
77 #define APMG_CLK_CTRL_REG (APMG_BASE + 0x0000)
78 #define APMG_CLK_EN_REG (APMG_BASE + 0x0004)
79 #define APMG_CLK_DIS_REG (APMG_BASE + 0x0008)
80 #define APMG_PS_CTRL_REG (APMG_BASE + 0x000c)
81 #define APMG_PCIDEV_STT_REG (APMG_BASE + 0x0010)
82 #define APMG_RFKILL_REG (APMG_BASE + 0x0014)
83 #define APMG_RTC_INT_STT_REG (APMG_BASE + 0x001c)
84 #define APMG_RTC_INT_MSK_REG (APMG_BASE + 0x0020)
85 #define APMG_DIGITAL_SVR_REG (APMG_BASE + 0x0058)
86 #define APMG_ANALOG_SVR_REG (APMG_BASE + 0x006C)
87
88 #define APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001)
89 #define APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)
90 #define APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)
91
92 #define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000)
93 #define APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)
94 #define APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)
95 #define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)
96 #define APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000)
97 #define APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */
98 #define APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060)
99
100 #define APMG_PCIDEV_STT_VAL_PERSIST_DIS (0x00000200)
101 #define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
102
103 #define APMG_RTC_INT_STT_RFKILL (0x10000000)
104
105 /* Device system time */
106 #define DEVICE_SYSTEM_TIME_REG 0xA0206C
107
108 /* Device NMI register */
109 #define DEVICE_SET_NMI_REG 0x00a01c30
110 #define DEVICE_SET_NMI_VAL 0x1
111 #define DEVICE_SET_NMI_8000B_REG 0x00a01c24
112 #define DEVICE_SET_NMI_8000B_VAL 0x1000000
113
114 /* Shared registers (0x0..0x3ff, via target indirect or periphery */
115 #define SHR_BASE 0x00a10000
116
117 /* Shared GP1 register */
118 #define SHR_APMG_GP1_REG 0x01dc
119 #define SHR_APMG_GP1_REG_PRPH (SHR_BASE + SHR_APMG_GP1_REG)
120 #define SHR_APMG_GP1_WF_XTAL_LP_EN 0x00000004
121 #define SHR_APMG_GP1_CHICKEN_BIT_SELECT 0x80000000
122
123 /* Shared DL_CFG register */
124 #define SHR_APMG_DL_CFG_REG 0x01c4
125 #define SHR_APMG_DL_CFG_REG_PRPH (SHR_BASE + SHR_APMG_DL_CFG_REG)
126 #define SHR_APMG_DL_CFG_RTCS_CLK_SELECTOR_MSK 0x000000c0
127 #define SHR_APMG_DL_CFG_RTCS_CLK_INTERNAL_XTAL 0x00000080
128 #define SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP 0x00000100
129
130 /* Shared APMG_XTAL_CFG register */
131 #define SHR_APMG_XTAL_CFG_REG 0x1c0
132 #define SHR_APMG_XTAL_CFG_XTAL_ON_REQ 0x80000000
133
134 /*
135 * Device reset for family 8000
136 * write to bit 24 in order to reset the CPU
137 */
138 #define RELEASE_CPU_RESET (0x300C)
139 #define RELEASE_CPU_RESET_BIT BIT(24)
140
141 /*****************************************************************************
142 * 7000/3000 series SHR DTS addresses *
143 *****************************************************************************/
144
145 #define SHR_MISC_WFM_DTS_EN (0x00a10024)
146 #define DTSC_CFG_MODE (0x00a10604)
147 #define DTSC_VREF_AVG (0x00a10648)
148 #define DTSC_VREF5_AVG (0x00a1064c)
149 #define DTSC_CFG_MODE_PERIODIC (0x2)
150 #define DTSC_PTAT_AVG (0x00a10650)
151
152
153 /**
154 * Tx Scheduler
155 *
156 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs
157 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in
158 * host DRAM. It steers each frame's Tx command (which contains the frame
159 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the
160 * device. A queue maps to only one (selectable by driver) Tx DMA channel,
161 * but one DMA channel may take input from several queues.
162 *
163 * Tx DMA FIFOs have dedicated purposes.
164 *
165 * For 5000 series and up, they are used differently
166 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c):
167 *
168 * 0 -- EDCA BK (background) frames, lowest priority
169 * 1 -- EDCA BE (best effort) frames, normal priority
170 * 2 -- EDCA VI (video) frames, higher priority
171 * 3 -- EDCA VO (voice) and management frames, highest priority
172 * 4 -- unused
173 * 5 -- unused
174 * 6 -- unused
175 * 7 -- Commands
176 *
177 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
178 * In addition, driver can map the remaining queues to Tx DMA/FIFO
179 * channels 0-3 to support 11n aggregation via EDCA DMA channels.
180 *
181 * The driver sets up each queue to work in one of two modes:
182 *
183 * 1) Scheduler-Ack, in which the scheduler automatically supports a
184 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue
185 * contains TFDs for a unique combination of Recipient Address (RA)
186 * and Traffic Identifier (TID), that is, traffic of a given
187 * Quality-Of-Service (QOS) priority, destined for a single station.
188 *
189 * In scheduler-ack mode, the scheduler keeps track of the Tx status of
190 * each frame within the BA window, including whether it's been transmitted,
191 * and whether it's been acknowledged by the receiving station. The device
192 * automatically processes block-acks received from the receiving STA,
193 * and reschedules un-acked frames to be retransmitted (successful
194 * Tx completion may end up being out-of-order).
195 *
196 * The driver must maintain the queue's Byte Count table in host DRAM
197 * for this mode.
198 * This mode does not support fragmentation.
199 *
200 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.
201 * The device may automatically retry Tx, but will retry only one frame
202 * at a time, until receiving ACK from receiving station, or reaching
203 * retry limit and giving up.
204 *
205 * The command queue (#4/#9) must use this mode!
206 * This mode does not require use of the Byte Count table in host DRAM.
207 *
208 * Driver controls scheduler operation via 3 means:
209 * 1) Scheduler registers
210 * 2) Shared scheduler data base in internal SRAM
211 * 3) Shared data in host DRAM
212 *
213 * Initialization:
214 *
215 * When loading, driver should allocate memory for:
216 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs.
217 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory
218 * (1024 bytes for each queue).
219 *
220 * After receiving "Alive" response from uCode, driver must initialize
221 * the scheduler (especially for queue #4/#9, the command queue, otherwise
222 * the driver can't issue commands!):
223 */
224 #define SCD_MEM_LOWER_BOUND (0x0000)
225
226 /**
227 * Max Tx window size is the max number of contiguous TFDs that the scheduler
228 * can keep track of at one time when creating block-ack chains of frames.
229 * Note that "64" matches the number of ack bits in a block-ack packet.
230 */
231 #define SCD_WIN_SIZE 64
232 #define SCD_FRAME_LIMIT 64
233
234 #define SCD_TXFIFO_POS_TID (0)
235 #define SCD_TXFIFO_POS_RA (4)
236 #define SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
237
238 /* agn SCD */
239 #define SCD_QUEUE_STTS_REG_POS_TXF (0)
240 #define SCD_QUEUE_STTS_REG_POS_ACTIVE (3)
241 #define SCD_QUEUE_STTS_REG_POS_WSL (4)
242 #define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19)
243 #define SCD_QUEUE_STTS_REG_MSK (0x017F0000)
244
245 #define SCD_QUEUE_CTX_REG1_CREDIT_POS (8)
246 #define SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00)
247 #define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24)
248 #define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000)
249 #define SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0)
250 #define SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F)
251 #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
252 #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
253
254 /* Context Data */
255 #define SCD_CONTEXT_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x600)
256 #define SCD_CONTEXT_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0)
257
258 /* Tx status */
259 #define SCD_TX_STTS_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0)
260 #define SCD_TX_STTS_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0)
261
262 /* Translation Data */
263 #define SCD_TRANS_TBL_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0)
264 #define SCD_TRANS_TBL_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x808)
265
266 #define SCD_CONTEXT_QUEUE_OFFSET(x)\
267 (SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8))
268
269 #define SCD_TX_STTS_QUEUE_OFFSET(x)\
270 (SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16))
271
272 #define SCD_TRANS_TBL_OFFSET_QUEUE(x) \
273 ((SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc)
274
275 #define SCD_BASE (PRPH_BASE + 0xa02c00)
276
277 #define SCD_SRAM_BASE_ADDR (SCD_BASE + 0x0)
278 #define SCD_DRAM_BASE_ADDR (SCD_BASE + 0x8)
279 #define SCD_AIT (SCD_BASE + 0x0c)
280 #define SCD_TXFACT (SCD_BASE + 0x10)
281 #define SCD_ACTIVE (SCD_BASE + 0x14)
282 #define SCD_QUEUECHAIN_SEL (SCD_BASE + 0xe8)
283 #define SCD_CHAINEXT_EN (SCD_BASE + 0x244)
284 #define SCD_AGGR_SEL (SCD_BASE + 0x248)
285 #define SCD_INTERRUPT_MASK (SCD_BASE + 0x108)
286 #define SCD_EN_CTRL (SCD_BASE + 0x254)
287
SCD_QUEUE_WRPTR(unsigned int chnl)288 static inline unsigned int SCD_QUEUE_WRPTR(unsigned int chnl)
289 {
290 if (chnl < 20)
291 return SCD_BASE + 0x18 + chnl * 4;
292 WARN_ON_ONCE(chnl >= 32);
293 return SCD_BASE + 0x284 + (chnl - 20) * 4;
294 }
295
SCD_QUEUE_RDPTR(unsigned int chnl)296 static inline unsigned int SCD_QUEUE_RDPTR(unsigned int chnl)
297 {
298 if (chnl < 20)
299 return SCD_BASE + 0x68 + chnl * 4;
300 WARN_ON_ONCE(chnl >= 32);
301 return SCD_BASE + 0x2B4 + (chnl - 20) * 4;
302 }
303
SCD_QUEUE_STATUS_BITS(unsigned int chnl)304 static inline unsigned int SCD_QUEUE_STATUS_BITS(unsigned int chnl)
305 {
306 if (chnl < 20)
307 return SCD_BASE + 0x10c + chnl * 4;
308 WARN_ON_ONCE(chnl >= 32);
309 return SCD_BASE + 0x384 + (chnl - 20) * 4;
310 }
311
312 /*********************** END TX SCHEDULER *************************************/
313
314 /* Oscillator clock */
315 #define OSC_CLK (0xa04068)
316 #define OSC_CLK_FORCE_CONTROL (0x8)
317
318 /* SECURE boot registers */
319 #define LMPM_SECURE_BOOT_CONFIG_ADDR (0x100)
320 enum secure_boot_config_reg {
321 LMPM_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001,
322 LMPM_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002,
323 };
324
325 #define LMPM_SECURE_BOOT_CPU1_STATUS_ADDR (0x1E30)
326 #define LMPM_SECURE_BOOT_CPU2_STATUS_ADDR (0x1E34)
327 enum secure_boot_status_reg {
328 LMPM_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000001,
329 LMPM_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002,
330 LMPM_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004,
331 LMPM_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008,
332 LMPM_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010,
333 LMPM_SECURE_BOOT_STATUS_SUCCESS = 0x00000003,
334 };
335
336 #define CSR_UCODE_LOAD_STATUS_ADDR (0x1E70)
337 enum secure_load_status_reg {
338 LMPM_CPU_UCODE_LOADING_STARTED = 0x00000001,
339 LMPM_CPU_HDRS_LOADING_COMPLETED = 0x00000003,
340 LMPM_CPU_UCODE_LOADING_COMPLETED = 0x00000007,
341 LMPM_CPU_STATUS_NUM_OF_LAST_COMPLETED = 0x000000F8,
342 LMPM_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK = 0x0000FF00,
343 };
344
345 #define LMPM_SECURE_INSPECTOR_CODE_ADDR (0x1E38)
346 #define LMPM_SECURE_INSPECTOR_DATA_ADDR (0x1E3C)
347 #define LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR (0x1E78)
348 #define LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR (0x1E7C)
349
350 #define LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE (0x400000)
351 #define LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE (0x402000)
352 #define LMPM_SECURE_CPU1_HDR_MEM_SPACE (0x420000)
353 #define LMPM_SECURE_CPU2_HDR_MEM_SPACE (0x420400)
354
355 #define LMPM_SECURE_TIME_OUT (100)
356
357 /* Rx FIFO */
358 #define RXF_SIZE_ADDR (0xa00c88)
359 #define RXF_SIZE_BYTE_CND_POS (7)
360 #define RXF_SIZE_BYTE_CNT_MSK (0x3ff << RXF_SIZE_BYTE_CND_POS)
361
362 #define RXF_LD_FENCE_OFFSET_ADDR (0xa00c10)
363 #define RXF_FIFO_RD_FENCE_ADDR (0xa00c0c)
364
365 /* FW monitor */
366 #define MON_BUFF_BASE_ADDR (0xa03c3c)
367 #define MON_BUFF_END_ADDR (0xa03c40)
368 #define MON_BUFF_WRPTR (0xa03c44)
369 #define MON_BUFF_CYCLE_CNT (0xa03c48)
370
371 /* FW chicken bits */
372 #define LMPM_CHICK 0xA01FF8
373 enum {
374 LMPM_CHICK_EXTENDED_ADDR_SPACE = BIT(0),
375 };
376
377 #endif /* __iwl_prph_h__ */
378