1 /*
2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
11 */
12 #undef DEBUG
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_reg.h>
21 #include <linux/serial_core.h>
22 #include <linux/8250_pci.h>
23 #include <linux/bitops.h>
24
25 #include <asm/byteorder.h>
26 #include <asm/io.h>
27
28 #include <linux/dmaengine.h>
29 #include <linux/platform_data/dma-dw.h>
30
31 #include "8250.h"
32
33 /*
34 * init function returns:
35 * > 0 - number of ports
36 * = 0 - use board->num_ports
37 * < 0 - error
38 */
39 struct pci_serial_quirk {
40 u32 vendor;
41 u32 device;
42 u32 subvendor;
43 u32 subdevice;
44 int (*probe)(struct pci_dev *dev);
45 int (*init)(struct pci_dev *dev);
46 int (*setup)(struct serial_private *,
47 const struct pciserial_board *,
48 struct uart_8250_port *, int);
49 void (*exit)(struct pci_dev *dev);
50 };
51
52 #define PCI_NUM_BAR_RESOURCES 6
53
54 struct serial_private {
55 struct pci_dev *dev;
56 unsigned int nr;
57 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
58 struct pci_serial_quirk *quirk;
59 const struct pciserial_board *board;
60 int line[0];
61 };
62
63 static int pci_default_setup(struct serial_private*,
64 const struct pciserial_board*, struct uart_8250_port *, int);
65
moan_device(const char * str,struct pci_dev * dev)66 static void moan_device(const char *str, struct pci_dev *dev)
67 {
68 dev_err(&dev->dev,
69 "%s: %s\n"
70 "Please send the output of lspci -vv, this\n"
71 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
72 "manufacturer and name of serial board or\n"
73 "modem board to <linux-serial@vger.kernel.org>.\n",
74 pci_name(dev), str, dev->vendor, dev->device,
75 dev->subsystem_vendor, dev->subsystem_device);
76 }
77
78 static int
setup_port(struct serial_private * priv,struct uart_8250_port * port,int bar,int offset,int regshift)79 setup_port(struct serial_private *priv, struct uart_8250_port *port,
80 int bar, int offset, int regshift)
81 {
82 struct pci_dev *dev = priv->dev;
83 unsigned long base, len;
84
85 if (bar >= PCI_NUM_BAR_RESOURCES)
86 return -EINVAL;
87
88 base = pci_resource_start(dev, bar);
89
90 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
91 len = pci_resource_len(dev, bar);
92
93 if (!priv->remapped_bar[bar])
94 priv->remapped_bar[bar] = ioremap_nocache(base, len);
95 if (!priv->remapped_bar[bar])
96 return -ENOMEM;
97
98 port->port.iotype = UPIO_MEM;
99 port->port.iobase = 0;
100 port->port.mapbase = base + offset;
101 port->port.membase = priv->remapped_bar[bar] + offset;
102 port->port.regshift = regshift;
103 } else {
104 port->port.iotype = UPIO_PORT;
105 port->port.iobase = base + offset;
106 port->port.mapbase = 0;
107 port->port.membase = NULL;
108 port->port.regshift = 0;
109 }
110 return 0;
111 }
112
113 /*
114 * ADDI-DATA GmbH communication cards <info@addi-data.com>
115 */
addidata_apci7800_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)116 static int addidata_apci7800_setup(struct serial_private *priv,
117 const struct pciserial_board *board,
118 struct uart_8250_port *port, int idx)
119 {
120 unsigned int bar = 0, offset = board->first_offset;
121 bar = FL_GET_BASE(board->flags);
122
123 if (idx < 2) {
124 offset += idx * board->uart_offset;
125 } else if ((idx >= 2) && (idx < 4)) {
126 bar += 1;
127 offset += ((idx - 2) * board->uart_offset);
128 } else if ((idx >= 4) && (idx < 6)) {
129 bar += 2;
130 offset += ((idx - 4) * board->uart_offset);
131 } else if (idx >= 6) {
132 bar += 3;
133 offset += ((idx - 6) * board->uart_offset);
134 }
135
136 return setup_port(priv, port, bar, offset, board->reg_shift);
137 }
138
139 /*
140 * AFAVLAB uses a different mixture of BARs and offsets
141 * Not that ugly ;) -- HW
142 */
143 static int
afavlab_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)144 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
145 struct uart_8250_port *port, int idx)
146 {
147 unsigned int bar, offset = board->first_offset;
148
149 bar = FL_GET_BASE(board->flags);
150 if (idx < 4)
151 bar += idx;
152 else {
153 bar = 4;
154 offset += (idx - 4) * board->uart_offset;
155 }
156
157 return setup_port(priv, port, bar, offset, board->reg_shift);
158 }
159
160 /*
161 * HP's Remote Management Console. The Diva chip came in several
162 * different versions. N-class, L2000 and A500 have two Diva chips, each
163 * with 3 UARTs (the third UART on the second chip is unused). Superdome
164 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
165 * one Diva chip, but it has been expanded to 5 UARTs.
166 */
pci_hp_diva_init(struct pci_dev * dev)167 static int pci_hp_diva_init(struct pci_dev *dev)
168 {
169 int rc = 0;
170
171 switch (dev->subsystem_device) {
172 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
173 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
174 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
175 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
176 rc = 3;
177 break;
178 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
179 rc = 2;
180 break;
181 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
182 rc = 4;
183 break;
184 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
185 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
186 rc = 1;
187 break;
188 }
189
190 return rc;
191 }
192
193 /*
194 * HP's Diva chip puts the 4th/5th serial port further out, and
195 * some serial ports are supposed to be hidden on certain models.
196 */
197 static int
pci_hp_diva_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)198 pci_hp_diva_setup(struct serial_private *priv,
199 const struct pciserial_board *board,
200 struct uart_8250_port *port, int idx)
201 {
202 unsigned int offset = board->first_offset;
203 unsigned int bar = FL_GET_BASE(board->flags);
204
205 switch (priv->dev->subsystem_device) {
206 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
207 if (idx == 3)
208 idx++;
209 break;
210 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
211 if (idx > 0)
212 idx++;
213 if (idx > 2)
214 idx++;
215 break;
216 }
217 if (idx > 2)
218 offset = 0x18;
219
220 offset += idx * board->uart_offset;
221
222 return setup_port(priv, port, bar, offset, board->reg_shift);
223 }
224
225 /*
226 * Added for EKF Intel i960 serial boards
227 */
pci_inteli960ni_init(struct pci_dev * dev)228 static int pci_inteli960ni_init(struct pci_dev *dev)
229 {
230 unsigned long oldval;
231
232 if (!(dev->subsystem_device & 0x1000))
233 return -ENODEV;
234
235 /* is firmware started? */
236 pci_read_config_dword(dev, 0x44, (void *)&oldval);
237 if (oldval == 0x00001000L) { /* RESET value */
238 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
239 return -ENODEV;
240 }
241 return 0;
242 }
243
244 /*
245 * Some PCI serial cards using the PLX 9050 PCI interface chip require
246 * that the card interrupt be explicitly enabled or disabled. This
247 * seems to be mainly needed on card using the PLX which also use I/O
248 * mapped memory.
249 */
pci_plx9050_init(struct pci_dev * dev)250 static int pci_plx9050_init(struct pci_dev *dev)
251 {
252 u8 irq_config;
253 void __iomem *p;
254
255 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
256 moan_device("no memory in bar 0", dev);
257 return 0;
258 }
259
260 irq_config = 0x41;
261 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
262 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
263 irq_config = 0x43;
264
265 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
266 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
267 /*
268 * As the megawolf cards have the int pins active
269 * high, and have 2 UART chips, both ints must be
270 * enabled on the 9050. Also, the UARTS are set in
271 * 16450 mode by default, so we have to enable the
272 * 16C950 'enhanced' mode so that we can use the
273 * deep FIFOs
274 */
275 irq_config = 0x5b;
276 /*
277 * enable/disable interrupts
278 */
279 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
280 if (p == NULL)
281 return -ENOMEM;
282 writel(irq_config, p + 0x4c);
283
284 /*
285 * Read the register back to ensure that it took effect.
286 */
287 readl(p + 0x4c);
288 iounmap(p);
289
290 return 0;
291 }
292
pci_plx9050_exit(struct pci_dev * dev)293 static void pci_plx9050_exit(struct pci_dev *dev)
294 {
295 u8 __iomem *p;
296
297 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
298 return;
299
300 /*
301 * disable interrupts
302 */
303 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
304 if (p != NULL) {
305 writel(0, p + 0x4c);
306
307 /*
308 * Read the register back to ensure that it took effect.
309 */
310 readl(p + 0x4c);
311 iounmap(p);
312 }
313 }
314
315 #define NI8420_INT_ENABLE_REG 0x38
316 #define NI8420_INT_ENABLE_BIT 0x2000
317
pci_ni8420_exit(struct pci_dev * dev)318 static void pci_ni8420_exit(struct pci_dev *dev)
319 {
320 void __iomem *p;
321 unsigned long base, len;
322 unsigned int bar = 0;
323
324 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
325 moan_device("no memory in bar", dev);
326 return;
327 }
328
329 base = pci_resource_start(dev, bar);
330 len = pci_resource_len(dev, bar);
331 p = ioremap_nocache(base, len);
332 if (p == NULL)
333 return;
334
335 /* Disable the CPU Interrupt */
336 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
337 p + NI8420_INT_ENABLE_REG);
338 iounmap(p);
339 }
340
341
342 /* MITE registers */
343 #define MITE_IOWBSR1 0xc4
344 #define MITE_IOWCR1 0xf4
345 #define MITE_LCIMR1 0x08
346 #define MITE_LCIMR2 0x10
347
348 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
349
pci_ni8430_exit(struct pci_dev * dev)350 static void pci_ni8430_exit(struct pci_dev *dev)
351 {
352 void __iomem *p;
353 unsigned long base, len;
354 unsigned int bar = 0;
355
356 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
357 moan_device("no memory in bar", dev);
358 return;
359 }
360
361 base = pci_resource_start(dev, bar);
362 len = pci_resource_len(dev, bar);
363 p = ioremap_nocache(base, len);
364 if (p == NULL)
365 return;
366
367 /* Disable the CPU Interrupt */
368 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
369 iounmap(p);
370 }
371
372 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
373 static int
sbs_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)374 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
375 struct uart_8250_port *port, int idx)
376 {
377 unsigned int bar, offset = board->first_offset;
378
379 bar = 0;
380
381 if (idx < 4) {
382 /* first four channels map to 0, 0x100, 0x200, 0x300 */
383 offset += idx * board->uart_offset;
384 } else if (idx < 8) {
385 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
386 offset += idx * board->uart_offset + 0xC00;
387 } else /* we have only 8 ports on PMC-OCTALPRO */
388 return 1;
389
390 return setup_port(priv, port, bar, offset, board->reg_shift);
391 }
392
393 /*
394 * This does initialization for PMC OCTALPRO cards:
395 * maps the device memory, resets the UARTs (needed, bc
396 * if the module is removed and inserted again, the card
397 * is in the sleep mode) and enables global interrupt.
398 */
399
400 /* global control register offset for SBS PMC-OctalPro */
401 #define OCT_REG_CR_OFF 0x500
402
sbs_init(struct pci_dev * dev)403 static int sbs_init(struct pci_dev *dev)
404 {
405 u8 __iomem *p;
406
407 p = pci_ioremap_bar(dev, 0);
408
409 if (p == NULL)
410 return -ENOMEM;
411 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
412 writeb(0x10, p + OCT_REG_CR_OFF);
413 udelay(50);
414 writeb(0x0, p + OCT_REG_CR_OFF);
415
416 /* Set bit-2 (INTENABLE) of Control Register */
417 writeb(0x4, p + OCT_REG_CR_OFF);
418 iounmap(p);
419
420 return 0;
421 }
422
423 /*
424 * Disables the global interrupt of PMC-OctalPro
425 */
426
sbs_exit(struct pci_dev * dev)427 static void sbs_exit(struct pci_dev *dev)
428 {
429 u8 __iomem *p;
430
431 p = pci_ioremap_bar(dev, 0);
432 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
433 if (p != NULL)
434 writeb(0, p + OCT_REG_CR_OFF);
435 iounmap(p);
436 }
437
438 /*
439 * SIIG serial cards have an PCI interface chip which also controls
440 * the UART clocking frequency. Each UART can be clocked independently
441 * (except cards equipped with 4 UARTs) and initial clocking settings
442 * are stored in the EEPROM chip. It can cause problems because this
443 * version of serial driver doesn't support differently clocked UART's
444 * on single PCI card. To prevent this, initialization functions set
445 * high frequency clocking for all UART's on given card. It is safe (I
446 * hope) because it doesn't touch EEPROM settings to prevent conflicts
447 * with other OSes (like M$ DOS).
448 *
449 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
450 *
451 * There is two family of SIIG serial cards with different PCI
452 * interface chip and different configuration methods:
453 * - 10x cards have control registers in IO and/or memory space;
454 * - 20x cards have control registers in standard PCI configuration space.
455 *
456 * Note: all 10x cards have PCI device ids 0x10..
457 * all 20x cards have PCI device ids 0x20..
458 *
459 * There are also Quartet Serial cards which use Oxford Semiconductor
460 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
461 *
462 * Note: some SIIG cards are probed by the parport_serial object.
463 */
464
465 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
466 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
467
pci_siig10x_init(struct pci_dev * dev)468 static int pci_siig10x_init(struct pci_dev *dev)
469 {
470 u16 data;
471 void __iomem *p;
472
473 switch (dev->device & 0xfff8) {
474 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
475 data = 0xffdf;
476 break;
477 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
478 data = 0xf7ff;
479 break;
480 default: /* 1S1P, 4S */
481 data = 0xfffb;
482 break;
483 }
484
485 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
486 if (p == NULL)
487 return -ENOMEM;
488
489 writew(readw(p + 0x28) & data, p + 0x28);
490 readw(p + 0x28);
491 iounmap(p);
492 return 0;
493 }
494
495 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
496 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
497
pci_siig20x_init(struct pci_dev * dev)498 static int pci_siig20x_init(struct pci_dev *dev)
499 {
500 u8 data;
501
502 /* Change clock frequency for the first UART. */
503 pci_read_config_byte(dev, 0x6f, &data);
504 pci_write_config_byte(dev, 0x6f, data & 0xef);
505
506 /* If this card has 2 UART, we have to do the same with second UART. */
507 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
508 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
509 pci_read_config_byte(dev, 0x73, &data);
510 pci_write_config_byte(dev, 0x73, data & 0xef);
511 }
512 return 0;
513 }
514
pci_siig_init(struct pci_dev * dev)515 static int pci_siig_init(struct pci_dev *dev)
516 {
517 unsigned int type = dev->device & 0xff00;
518
519 if (type == 0x1000)
520 return pci_siig10x_init(dev);
521 else if (type == 0x2000)
522 return pci_siig20x_init(dev);
523
524 moan_device("Unknown SIIG card", dev);
525 return -ENODEV;
526 }
527
pci_siig_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)528 static int pci_siig_setup(struct serial_private *priv,
529 const struct pciserial_board *board,
530 struct uart_8250_port *port, int idx)
531 {
532 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
533
534 if (idx > 3) {
535 bar = 4;
536 offset = (idx - 4) * 8;
537 }
538
539 return setup_port(priv, port, bar, offset, 0);
540 }
541
542 /*
543 * Timedia has an explosion of boards, and to avoid the PCI table from
544 * growing *huge*, we use this function to collapse some 70 entries
545 * in the PCI table into one, for sanity's and compactness's sake.
546 */
547 static const unsigned short timedia_single_port[] = {
548 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
549 };
550
551 static const unsigned short timedia_dual_port[] = {
552 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
553 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
554 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
555 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
556 0xD079, 0
557 };
558
559 static const unsigned short timedia_quad_port[] = {
560 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
561 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
562 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
563 0xB157, 0
564 };
565
566 static const unsigned short timedia_eight_port[] = {
567 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
568 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
569 };
570
571 static const struct timedia_struct {
572 int num;
573 const unsigned short *ids;
574 } timedia_data[] = {
575 { 1, timedia_single_port },
576 { 2, timedia_dual_port },
577 { 4, timedia_quad_port },
578 { 8, timedia_eight_port }
579 };
580
581 /*
582 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
583 * listing them individually, this driver merely grabs them all with
584 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
585 * and should be left free to be claimed by parport_serial instead.
586 */
pci_timedia_probe(struct pci_dev * dev)587 static int pci_timedia_probe(struct pci_dev *dev)
588 {
589 /*
590 * Check the third digit of the subdevice ID
591 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
592 */
593 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
594 dev_info(&dev->dev,
595 "ignoring Timedia subdevice %04x for parport_serial\n",
596 dev->subsystem_device);
597 return -ENODEV;
598 }
599
600 return 0;
601 }
602
pci_timedia_init(struct pci_dev * dev)603 static int pci_timedia_init(struct pci_dev *dev)
604 {
605 const unsigned short *ids;
606 int i, j;
607
608 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
609 ids = timedia_data[i].ids;
610 for (j = 0; ids[j]; j++)
611 if (dev->subsystem_device == ids[j])
612 return timedia_data[i].num;
613 }
614 return 0;
615 }
616
617 /*
618 * Timedia/SUNIX uses a mixture of BARs and offsets
619 * Ugh, this is ugly as all hell --- TYT
620 */
621 static int
pci_timedia_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)622 pci_timedia_setup(struct serial_private *priv,
623 const struct pciserial_board *board,
624 struct uart_8250_port *port, int idx)
625 {
626 unsigned int bar = 0, offset = board->first_offset;
627
628 switch (idx) {
629 case 0:
630 bar = 0;
631 break;
632 case 1:
633 offset = board->uart_offset;
634 bar = 0;
635 break;
636 case 2:
637 bar = 1;
638 break;
639 case 3:
640 offset = board->uart_offset;
641 /* FALLTHROUGH */
642 case 4: /* BAR 2 */
643 case 5: /* BAR 3 */
644 case 6: /* BAR 4 */
645 case 7: /* BAR 5 */
646 bar = idx - 2;
647 }
648
649 return setup_port(priv, port, bar, offset, board->reg_shift);
650 }
651
652 /*
653 * Some Titan cards are also a little weird
654 */
655 static int
titan_400l_800l_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)656 titan_400l_800l_setup(struct serial_private *priv,
657 const struct pciserial_board *board,
658 struct uart_8250_port *port, int idx)
659 {
660 unsigned int bar, offset = board->first_offset;
661
662 switch (idx) {
663 case 0:
664 bar = 1;
665 break;
666 case 1:
667 bar = 2;
668 break;
669 default:
670 bar = 4;
671 offset = (idx - 2) * board->uart_offset;
672 }
673
674 return setup_port(priv, port, bar, offset, board->reg_shift);
675 }
676
pci_xircom_init(struct pci_dev * dev)677 static int pci_xircom_init(struct pci_dev *dev)
678 {
679 msleep(100);
680 return 0;
681 }
682
pci_ni8420_init(struct pci_dev * dev)683 static int pci_ni8420_init(struct pci_dev *dev)
684 {
685 void __iomem *p;
686 unsigned long base, len;
687 unsigned int bar = 0;
688
689 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
690 moan_device("no memory in bar", dev);
691 return 0;
692 }
693
694 base = pci_resource_start(dev, bar);
695 len = pci_resource_len(dev, bar);
696 p = ioremap_nocache(base, len);
697 if (p == NULL)
698 return -ENOMEM;
699
700 /* Enable CPU Interrupt */
701 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
702 p + NI8420_INT_ENABLE_REG);
703
704 iounmap(p);
705 return 0;
706 }
707
708 #define MITE_IOWBSR1_WSIZE 0xa
709 #define MITE_IOWBSR1_WIN_OFFSET 0x800
710 #define MITE_IOWBSR1_WENAB (1 << 7)
711 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
712 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
713 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
714
pci_ni8430_init(struct pci_dev * dev)715 static int pci_ni8430_init(struct pci_dev *dev)
716 {
717 void __iomem *p;
718 unsigned long base, len;
719 u32 device_window;
720 unsigned int bar = 0;
721
722 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
723 moan_device("no memory in bar", dev);
724 return 0;
725 }
726
727 base = pci_resource_start(dev, bar);
728 len = pci_resource_len(dev, bar);
729 p = ioremap_nocache(base, len);
730 if (p == NULL)
731 return -ENOMEM;
732
733 /* Set device window address and size in BAR0 */
734 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
735 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
736 writel(device_window, p + MITE_IOWBSR1);
737
738 /* Set window access to go to RAMSEL IO address space */
739 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
740 p + MITE_IOWCR1);
741
742 /* Enable IO Bus Interrupt 0 */
743 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
744
745 /* Enable CPU Interrupt */
746 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
747
748 iounmap(p);
749 return 0;
750 }
751
752 /* UART Port Control Register */
753 #define NI8430_PORTCON 0x0f
754 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
755
756 static int
pci_ni8430_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)757 pci_ni8430_setup(struct serial_private *priv,
758 const struct pciserial_board *board,
759 struct uart_8250_port *port, int idx)
760 {
761 void __iomem *p;
762 unsigned long base, len;
763 unsigned int bar, offset = board->first_offset;
764
765 if (idx >= board->num_ports)
766 return 1;
767
768 bar = FL_GET_BASE(board->flags);
769 offset += idx * board->uart_offset;
770
771 base = pci_resource_start(priv->dev, bar);
772 len = pci_resource_len(priv->dev, bar);
773 p = ioremap_nocache(base, len);
774
775 /* enable the transceiver */
776 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
777 p + offset + NI8430_PORTCON);
778
779 iounmap(p);
780
781 return setup_port(priv, port, bar, offset, board->reg_shift);
782 }
783
pci_netmos_9900_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)784 static int pci_netmos_9900_setup(struct serial_private *priv,
785 const struct pciserial_board *board,
786 struct uart_8250_port *port, int idx)
787 {
788 unsigned int bar;
789
790 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
791 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
792 /* netmos apparently orders BARs by datasheet layout, so serial
793 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
794 */
795 bar = 3 * idx;
796
797 return setup_port(priv, port, bar, 0, board->reg_shift);
798 } else {
799 return pci_default_setup(priv, board, port, idx);
800 }
801 }
802
803 /* the 99xx series comes with a range of device IDs and a variety
804 * of capabilities:
805 *
806 * 9900 has varying capabilities and can cascade to sub-controllers
807 * (cascading should be purely internal)
808 * 9904 is hardwired with 4 serial ports
809 * 9912 and 9922 are hardwired with 2 serial ports
810 */
pci_netmos_9900_numports(struct pci_dev * dev)811 static int pci_netmos_9900_numports(struct pci_dev *dev)
812 {
813 unsigned int c = dev->class;
814 unsigned int pi;
815 unsigned short sub_serports;
816
817 pi = (c & 0xff);
818
819 if (pi == 2) {
820 return 1;
821 } else if ((pi == 0) &&
822 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
823 /* two possibilities: 0x30ps encodes number of parallel and
824 * serial ports, or 0x1000 indicates *something*. This is not
825 * immediately obvious, since the 2s1p+4s configuration seems
826 * to offer all functionality on functions 0..2, while still
827 * advertising the same function 3 as the 4s+2s1p config.
828 */
829 sub_serports = dev->subsystem_device & 0xf;
830 if (sub_serports > 0) {
831 return sub_serports;
832 } else {
833 dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
834 return 0;
835 }
836 }
837
838 moan_device("unknown NetMos/Mostech program interface", dev);
839 return 0;
840 }
841
pci_netmos_init(struct pci_dev * dev)842 static int pci_netmos_init(struct pci_dev *dev)
843 {
844 /* subdevice 0x00PS means <P> parallel, <S> serial */
845 unsigned int num_serial = dev->subsystem_device & 0xf;
846
847 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
848 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
849 return 0;
850
851 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
852 dev->subsystem_device == 0x0299)
853 return 0;
854
855 switch (dev->device) { /* FALLTHROUGH on all */
856 case PCI_DEVICE_ID_NETMOS_9904:
857 case PCI_DEVICE_ID_NETMOS_9912:
858 case PCI_DEVICE_ID_NETMOS_9922:
859 case PCI_DEVICE_ID_NETMOS_9900:
860 num_serial = pci_netmos_9900_numports(dev);
861 break;
862
863 default:
864 if (num_serial == 0 ) {
865 moan_device("unknown NetMos/Mostech device", dev);
866 }
867 }
868
869 if (num_serial == 0)
870 return -ENODEV;
871
872 return num_serial;
873 }
874
875 /*
876 * These chips are available with optionally one parallel port and up to
877 * two serial ports. Unfortunately they all have the same product id.
878 *
879 * Basic configuration is done over a region of 32 I/O ports. The base
880 * ioport is called INTA or INTC, depending on docs/other drivers.
881 *
882 * The region of the 32 I/O ports is configured in POSIO0R...
883 */
884
885 /* registers */
886 #define ITE_887x_MISCR 0x9c
887 #define ITE_887x_INTCBAR 0x78
888 #define ITE_887x_UARTBAR 0x7c
889 #define ITE_887x_PS0BAR 0x10
890 #define ITE_887x_POSIO0 0x60
891
892 /* I/O space size */
893 #define ITE_887x_IOSIZE 32
894 /* I/O space size (bits 26-24; 8 bytes = 011b) */
895 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
896 /* I/O space size (bits 26-24; 32 bytes = 101b) */
897 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
898 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
899 #define ITE_887x_POSIO_SPEED (3 << 29)
900 /* enable IO_Space bit */
901 #define ITE_887x_POSIO_ENABLE (1 << 31)
902
pci_ite887x_init(struct pci_dev * dev)903 static int pci_ite887x_init(struct pci_dev *dev)
904 {
905 /* inta_addr are the configuration addresses of the ITE */
906 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
907 0x200, 0x280, 0 };
908 int ret, i, type;
909 struct resource *iobase = NULL;
910 u32 miscr, uartbar, ioport;
911
912 /* search for the base-ioport */
913 i = 0;
914 while (inta_addr[i] && iobase == NULL) {
915 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
916 "ite887x");
917 if (iobase != NULL) {
918 /* write POSIO0R - speed | size | ioport */
919 pci_write_config_dword(dev, ITE_887x_POSIO0,
920 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
921 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
922 /* write INTCBAR - ioport */
923 pci_write_config_dword(dev, ITE_887x_INTCBAR,
924 inta_addr[i]);
925 ret = inb(inta_addr[i]);
926 if (ret != 0xff) {
927 /* ioport connected */
928 break;
929 }
930 release_region(iobase->start, ITE_887x_IOSIZE);
931 iobase = NULL;
932 }
933 i++;
934 }
935
936 if (!inta_addr[i]) {
937 dev_err(&dev->dev, "ite887x: could not find iobase\n");
938 return -ENODEV;
939 }
940
941 /* start of undocumented type checking (see parport_pc.c) */
942 type = inb(iobase->start + 0x18) & 0x0f;
943
944 switch (type) {
945 case 0x2: /* ITE8871 (1P) */
946 case 0xa: /* ITE8875 (1P) */
947 ret = 0;
948 break;
949 case 0xe: /* ITE8872 (2S1P) */
950 ret = 2;
951 break;
952 case 0x6: /* ITE8873 (1S) */
953 ret = 1;
954 break;
955 case 0x8: /* ITE8874 (2S) */
956 ret = 2;
957 break;
958 default:
959 moan_device("Unknown ITE887x", dev);
960 ret = -ENODEV;
961 }
962
963 /* configure all serial ports */
964 for (i = 0; i < ret; i++) {
965 /* read the I/O port from the device */
966 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
967 &ioport);
968 ioport &= 0x0000FF00; /* the actual base address */
969 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
970 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
971 ITE_887x_POSIO_IOSIZE_8 | ioport);
972
973 /* write the ioport to the UARTBAR */
974 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
975 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
976 uartbar |= (ioport << (16 * i)); /* set the ioport */
977 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
978
979 /* get current config */
980 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
981 /* disable interrupts (UARTx_Routing[3:0]) */
982 miscr &= ~(0xf << (12 - 4 * i));
983 /* activate the UART (UARTx_En) */
984 miscr |= 1 << (23 - i);
985 /* write new config with activated UART */
986 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
987 }
988
989 if (ret <= 0) {
990 /* the device has no UARTs if we get here */
991 release_region(iobase->start, ITE_887x_IOSIZE);
992 }
993
994 return ret;
995 }
996
pci_ite887x_exit(struct pci_dev * dev)997 static void pci_ite887x_exit(struct pci_dev *dev)
998 {
999 u32 ioport;
1000 /* the ioport is bit 0-15 in POSIO0R */
1001 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
1002 ioport &= 0xffff;
1003 release_region(ioport, ITE_887x_IOSIZE);
1004 }
1005
1006 /*
1007 * Oxford Semiconductor Inc.
1008 * Check that device is part of the Tornado range of devices, then determine
1009 * the number of ports available on the device.
1010 */
pci_oxsemi_tornado_init(struct pci_dev * dev)1011 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1012 {
1013 u8 __iomem *p;
1014 unsigned long deviceID;
1015 unsigned int number_uarts = 0;
1016
1017 /* OxSemi Tornado devices are all 0xCxxx */
1018 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1019 (dev->device & 0xF000) != 0xC000)
1020 return 0;
1021
1022 p = pci_iomap(dev, 0, 5);
1023 if (p == NULL)
1024 return -ENOMEM;
1025
1026 deviceID = ioread32(p);
1027 /* Tornado device */
1028 if (deviceID == 0x07000200) {
1029 number_uarts = ioread8(p + 4);
1030 dev_dbg(&dev->dev,
1031 "%d ports detected on Oxford PCI Express device\n",
1032 number_uarts);
1033 }
1034 pci_iounmap(dev, p);
1035 return number_uarts;
1036 }
1037
pci_asix_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1038 static int pci_asix_setup(struct serial_private *priv,
1039 const struct pciserial_board *board,
1040 struct uart_8250_port *port, int idx)
1041 {
1042 port->bugs |= UART_BUG_PARITY;
1043 return pci_default_setup(priv, board, port, idx);
1044 }
1045
1046 /* Quatech devices have their own extra interface features */
1047
1048 struct quatech_feature {
1049 u16 devid;
1050 bool amcc;
1051 };
1052
1053 #define QPCR_TEST_FOR1 0x3F
1054 #define QPCR_TEST_GET1 0x00
1055 #define QPCR_TEST_FOR2 0x40
1056 #define QPCR_TEST_GET2 0x40
1057 #define QPCR_TEST_FOR3 0x80
1058 #define QPCR_TEST_GET3 0x40
1059 #define QPCR_TEST_FOR4 0xC0
1060 #define QPCR_TEST_GET4 0x80
1061
1062 #define QOPR_CLOCK_X1 0x0000
1063 #define QOPR_CLOCK_X2 0x0001
1064 #define QOPR_CLOCK_X4 0x0002
1065 #define QOPR_CLOCK_X8 0x0003
1066 #define QOPR_CLOCK_RATE_MASK 0x0003
1067
1068
1069 static struct quatech_feature quatech_cards[] = {
1070 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1071 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1072 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1073 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1074 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1075 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1076 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1077 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1078 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1079 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1080 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1081 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1082 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1083 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1084 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1085 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1086 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1087 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1088 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1089 { 0, }
1090 };
1091
pci_quatech_amcc(u16 devid)1092 static int pci_quatech_amcc(u16 devid)
1093 {
1094 struct quatech_feature *qf = &quatech_cards[0];
1095 while (qf->devid) {
1096 if (qf->devid == devid)
1097 return qf->amcc;
1098 qf++;
1099 }
1100 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1101 return 0;
1102 };
1103
pci_quatech_rqopr(struct uart_8250_port * port)1104 static int pci_quatech_rqopr(struct uart_8250_port *port)
1105 {
1106 unsigned long base = port->port.iobase;
1107 u8 LCR, val;
1108
1109 LCR = inb(base + UART_LCR);
1110 outb(0xBF, base + UART_LCR);
1111 val = inb(base + UART_SCR);
1112 outb(LCR, base + UART_LCR);
1113 return val;
1114 }
1115
pci_quatech_wqopr(struct uart_8250_port * port,u8 qopr)1116 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1117 {
1118 unsigned long base = port->port.iobase;
1119 u8 LCR, val;
1120
1121 LCR = inb(base + UART_LCR);
1122 outb(0xBF, base + UART_LCR);
1123 val = inb(base + UART_SCR);
1124 outb(qopr, base + UART_SCR);
1125 outb(LCR, base + UART_LCR);
1126 }
1127
pci_quatech_rqmcr(struct uart_8250_port * port)1128 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1129 {
1130 unsigned long base = port->port.iobase;
1131 u8 LCR, val, qmcr;
1132
1133 LCR = inb(base + UART_LCR);
1134 outb(0xBF, base + UART_LCR);
1135 val = inb(base + UART_SCR);
1136 outb(val | 0x10, base + UART_SCR);
1137 qmcr = inb(base + UART_MCR);
1138 outb(val, base + UART_SCR);
1139 outb(LCR, base + UART_LCR);
1140
1141 return qmcr;
1142 }
1143
pci_quatech_wqmcr(struct uart_8250_port * port,u8 qmcr)1144 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1145 {
1146 unsigned long base = port->port.iobase;
1147 u8 LCR, val;
1148
1149 LCR = inb(base + UART_LCR);
1150 outb(0xBF, base + UART_LCR);
1151 val = inb(base + UART_SCR);
1152 outb(val | 0x10, base + UART_SCR);
1153 outb(qmcr, base + UART_MCR);
1154 outb(val, base + UART_SCR);
1155 outb(LCR, base + UART_LCR);
1156 }
1157
pci_quatech_has_qmcr(struct uart_8250_port * port)1158 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1159 {
1160 unsigned long base = port->port.iobase;
1161 u8 LCR, val;
1162
1163 LCR = inb(base + UART_LCR);
1164 outb(0xBF, base + UART_LCR);
1165 val = inb(base + UART_SCR);
1166 if (val & 0x20) {
1167 outb(0x80, UART_LCR);
1168 if (!(inb(UART_SCR) & 0x20)) {
1169 outb(LCR, base + UART_LCR);
1170 return 1;
1171 }
1172 }
1173 return 0;
1174 }
1175
pci_quatech_test(struct uart_8250_port * port)1176 static int pci_quatech_test(struct uart_8250_port *port)
1177 {
1178 u8 reg;
1179 u8 qopr = pci_quatech_rqopr(port);
1180 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1181 reg = pci_quatech_rqopr(port) & 0xC0;
1182 if (reg != QPCR_TEST_GET1)
1183 return -EINVAL;
1184 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1185 reg = pci_quatech_rqopr(port) & 0xC0;
1186 if (reg != QPCR_TEST_GET2)
1187 return -EINVAL;
1188 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1189 reg = pci_quatech_rqopr(port) & 0xC0;
1190 if (reg != QPCR_TEST_GET3)
1191 return -EINVAL;
1192 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1193 reg = pci_quatech_rqopr(port) & 0xC0;
1194 if (reg != QPCR_TEST_GET4)
1195 return -EINVAL;
1196
1197 pci_quatech_wqopr(port, qopr);
1198 return 0;
1199 }
1200
pci_quatech_clock(struct uart_8250_port * port)1201 static int pci_quatech_clock(struct uart_8250_port *port)
1202 {
1203 u8 qopr, reg, set;
1204 unsigned long clock;
1205
1206 if (pci_quatech_test(port) < 0)
1207 return 1843200;
1208
1209 qopr = pci_quatech_rqopr(port);
1210
1211 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1212 reg = pci_quatech_rqopr(port);
1213 if (reg & QOPR_CLOCK_X8) {
1214 clock = 1843200;
1215 goto out;
1216 }
1217 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1218 reg = pci_quatech_rqopr(port);
1219 if (!(reg & QOPR_CLOCK_X8)) {
1220 clock = 1843200;
1221 goto out;
1222 }
1223 reg &= QOPR_CLOCK_X8;
1224 if (reg == QOPR_CLOCK_X2) {
1225 clock = 3685400;
1226 set = QOPR_CLOCK_X2;
1227 } else if (reg == QOPR_CLOCK_X4) {
1228 clock = 7372800;
1229 set = QOPR_CLOCK_X4;
1230 } else if (reg == QOPR_CLOCK_X8) {
1231 clock = 14745600;
1232 set = QOPR_CLOCK_X8;
1233 } else {
1234 clock = 1843200;
1235 set = QOPR_CLOCK_X1;
1236 }
1237 qopr &= ~QOPR_CLOCK_RATE_MASK;
1238 qopr |= set;
1239
1240 out:
1241 pci_quatech_wqopr(port, qopr);
1242 return clock;
1243 }
1244
pci_quatech_rs422(struct uart_8250_port * port)1245 static int pci_quatech_rs422(struct uart_8250_port *port)
1246 {
1247 u8 qmcr;
1248 int rs422 = 0;
1249
1250 if (!pci_quatech_has_qmcr(port))
1251 return 0;
1252 qmcr = pci_quatech_rqmcr(port);
1253 pci_quatech_wqmcr(port, 0xFF);
1254 if (pci_quatech_rqmcr(port))
1255 rs422 = 1;
1256 pci_quatech_wqmcr(port, qmcr);
1257 return rs422;
1258 }
1259
pci_quatech_init(struct pci_dev * dev)1260 static int pci_quatech_init(struct pci_dev *dev)
1261 {
1262 if (pci_quatech_amcc(dev->device)) {
1263 unsigned long base = pci_resource_start(dev, 0);
1264 if (base) {
1265 u32 tmp;
1266 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1267 tmp = inl(base + 0x3c);
1268 outl(tmp | 0x01000000, base + 0x3c);
1269 outl(tmp &= ~0x01000000, base + 0x3c);
1270 }
1271 }
1272 return 0;
1273 }
1274
pci_quatech_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1275 static int pci_quatech_setup(struct serial_private *priv,
1276 const struct pciserial_board *board,
1277 struct uart_8250_port *port, int idx)
1278 {
1279 /* Needed by pci_quatech calls below */
1280 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1281 /* Set up the clocking */
1282 port->port.uartclk = pci_quatech_clock(port);
1283 /* For now just warn about RS422 */
1284 if (pci_quatech_rs422(port))
1285 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1286 return pci_default_setup(priv, board, port, idx);
1287 }
1288
pci_quatech_exit(struct pci_dev * dev)1289 static void pci_quatech_exit(struct pci_dev *dev)
1290 {
1291 }
1292
pci_default_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1293 static int pci_default_setup(struct serial_private *priv,
1294 const struct pciserial_board *board,
1295 struct uart_8250_port *port, int idx)
1296 {
1297 unsigned int bar, offset = board->first_offset, maxnr;
1298
1299 bar = FL_GET_BASE(board->flags);
1300 if (board->flags & FL_BASE_BARS)
1301 bar += idx;
1302 else
1303 offset += idx * board->uart_offset;
1304
1305 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1306 (board->reg_shift + 3);
1307
1308 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1309 return 1;
1310
1311 return setup_port(priv, port, bar, offset, board->reg_shift);
1312 }
1313
pci_pericom_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1314 static int pci_pericom_setup(struct serial_private *priv,
1315 const struct pciserial_board *board,
1316 struct uart_8250_port *port, int idx)
1317 {
1318 unsigned int bar, offset = board->first_offset, maxnr;
1319
1320 bar = FL_GET_BASE(board->flags);
1321 if (board->flags & FL_BASE_BARS)
1322 bar += idx;
1323 else
1324 offset += idx * board->uart_offset;
1325
1326 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1327 (board->reg_shift + 3);
1328
1329 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1330 return 1;
1331
1332 port->port.uartclk = 14745600;
1333
1334 return setup_port(priv, port, bar, offset, board->reg_shift);
1335 }
1336
1337 static int
ce4100_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1338 ce4100_serial_setup(struct serial_private *priv,
1339 const struct pciserial_board *board,
1340 struct uart_8250_port *port, int idx)
1341 {
1342 int ret;
1343
1344 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1345 port->port.iotype = UPIO_MEM32;
1346 port->port.type = PORT_XSCALE;
1347 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1348 port->port.regshift = 2;
1349
1350 return ret;
1351 }
1352
1353 #define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
1354 #define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
1355
1356 #define PCI_DEVICE_ID_INTEL_BSW_UART1 0x228a
1357 #define PCI_DEVICE_ID_INTEL_BSW_UART2 0x228c
1358
1359 #define PCI_DEVICE_ID_INTEL_BDW_UART1 0x9ce3
1360 #define PCI_DEVICE_ID_INTEL_BDW_UART2 0x9ce4
1361
1362 #define BYT_PRV_CLK 0x800
1363 #define BYT_PRV_CLK_EN (1 << 0)
1364 #define BYT_PRV_CLK_M_VAL_SHIFT 1
1365 #define BYT_PRV_CLK_N_VAL_SHIFT 16
1366 #define BYT_PRV_CLK_UPDATE (1 << 31)
1367
1368 #define BYT_TX_OVF_INT 0x820
1369 #define BYT_TX_OVF_INT_MASK (1 << 1)
1370
1371 static void
byt_set_termios(struct uart_port * p,struct ktermios * termios,struct ktermios * old)1372 byt_set_termios(struct uart_port *p, struct ktermios *termios,
1373 struct ktermios *old)
1374 {
1375 unsigned int baud = tty_termios_baud_rate(termios);
1376 unsigned int m, n;
1377 u32 reg;
1378
1379 /*
1380 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1381 * dividers must be adjusted.
1382 *
1383 * uartclk = (m / n) * 100 MHz, where m <= n
1384 */
1385 switch (baud) {
1386 case 500000:
1387 case 1000000:
1388 case 2000000:
1389 case 4000000:
1390 m = 64;
1391 n = 100;
1392 p->uartclk = 64000000;
1393 break;
1394 case 3500000:
1395 m = 56;
1396 n = 100;
1397 p->uartclk = 56000000;
1398 break;
1399 case 1500000:
1400 case 3000000:
1401 m = 48;
1402 n = 100;
1403 p->uartclk = 48000000;
1404 break;
1405 case 2500000:
1406 m = 40;
1407 n = 100;
1408 p->uartclk = 40000000;
1409 break;
1410 default:
1411 m = 2304;
1412 n = 3125;
1413 p->uartclk = 73728000;
1414 }
1415
1416 /* Reset the clock */
1417 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1418 writel(reg, p->membase + BYT_PRV_CLK);
1419 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1420 writel(reg, p->membase + BYT_PRV_CLK);
1421
1422 serial8250_do_set_termios(p, termios, old);
1423 }
1424
byt_dma_filter(struct dma_chan * chan,void * param)1425 static bool byt_dma_filter(struct dma_chan *chan, void *param)
1426 {
1427 struct dw_dma_slave *dws = param;
1428
1429 if (dws->dma_dev != chan->device->dev)
1430 return false;
1431
1432 chan->private = dws;
1433 return true;
1434 }
1435
1436 static int
byt_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1437 byt_serial_setup(struct serial_private *priv,
1438 const struct pciserial_board *board,
1439 struct uart_8250_port *port, int idx)
1440 {
1441 struct pci_dev *pdev = priv->dev;
1442 struct device *dev = port->port.dev;
1443 struct uart_8250_dma *dma;
1444 struct dw_dma_slave *tx_param, *rx_param;
1445 struct pci_dev *dma_dev;
1446 int ret;
1447
1448 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1449 if (!dma)
1450 return -ENOMEM;
1451
1452 tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1453 if (!tx_param)
1454 return -ENOMEM;
1455
1456 rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1457 if (!rx_param)
1458 return -ENOMEM;
1459
1460 switch (pdev->device) {
1461 case PCI_DEVICE_ID_INTEL_BYT_UART1:
1462 case PCI_DEVICE_ID_INTEL_BSW_UART1:
1463 case PCI_DEVICE_ID_INTEL_BDW_UART1:
1464 rx_param->src_id = 3;
1465 tx_param->dst_id = 2;
1466 break;
1467 case PCI_DEVICE_ID_INTEL_BYT_UART2:
1468 case PCI_DEVICE_ID_INTEL_BSW_UART2:
1469 case PCI_DEVICE_ID_INTEL_BDW_UART2:
1470 rx_param->src_id = 5;
1471 tx_param->dst_id = 4;
1472 break;
1473 default:
1474 return -EINVAL;
1475 }
1476
1477 rx_param->src_master = 1;
1478 rx_param->dst_master = 0;
1479
1480 dma->rxconf.src_maxburst = 16;
1481
1482 tx_param->src_master = 1;
1483 tx_param->dst_master = 0;
1484
1485 dma->txconf.dst_maxburst = 16;
1486
1487 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1488 rx_param->dma_dev = &dma_dev->dev;
1489 tx_param->dma_dev = &dma_dev->dev;
1490
1491 dma->fn = byt_dma_filter;
1492 dma->rx_param = rx_param;
1493 dma->tx_param = tx_param;
1494
1495 ret = pci_default_setup(priv, board, port, idx);
1496 port->port.iotype = UPIO_MEM;
1497 port->port.type = PORT_16550A;
1498 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1499 port->port.set_termios = byt_set_termios;
1500 port->port.fifosize = 64;
1501 port->tx_loadsz = 64;
1502 port->dma = dma;
1503 port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1504
1505 /* Disable Tx counter interrupts */
1506 writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1507
1508 return ret;
1509 }
1510
1511 static int
pci_omegapci_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1512 pci_omegapci_setup(struct serial_private *priv,
1513 const struct pciserial_board *board,
1514 struct uart_8250_port *port, int idx)
1515 {
1516 return setup_port(priv, port, 2, idx * 8, 0);
1517 }
1518
1519 static int
pci_brcm_trumanage_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1520 pci_brcm_trumanage_setup(struct serial_private *priv,
1521 const struct pciserial_board *board,
1522 struct uart_8250_port *port, int idx)
1523 {
1524 int ret = pci_default_setup(priv, board, port, idx);
1525
1526 port->port.type = PORT_BRCM_TRUMANAGE;
1527 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1528 return ret;
1529 }
1530
pci_fintek_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1531 static int pci_fintek_setup(struct serial_private *priv,
1532 const struct pciserial_board *board,
1533 struct uart_8250_port *port, int idx)
1534 {
1535 struct pci_dev *pdev = priv->dev;
1536 unsigned long base;
1537 unsigned long iobase;
1538 unsigned long ciobase = 0;
1539 u8 config_base;
1540
1541 /*
1542 * We are supposed to be able to read these from the PCI config space,
1543 * but the values there don't seem to match what we need to use, so
1544 * just use these hard-coded values for now, as they are correct.
1545 */
1546 switch (idx) {
1547 case 0: iobase = 0xe000; config_base = 0x40; break;
1548 case 1: iobase = 0xe008; config_base = 0x48; break;
1549 case 2: iobase = 0xe010; config_base = 0x50; break;
1550 case 3: iobase = 0xe018; config_base = 0x58; break;
1551 case 4: iobase = 0xe020; config_base = 0x60; break;
1552 case 5: iobase = 0xe028; config_base = 0x68; break;
1553 case 6: iobase = 0xe030; config_base = 0x70; break;
1554 case 7: iobase = 0xe038; config_base = 0x78; break;
1555 case 8: iobase = 0xe040; config_base = 0x80; break;
1556 case 9: iobase = 0xe048; config_base = 0x88; break;
1557 case 10: iobase = 0xe050; config_base = 0x90; break;
1558 case 11: iobase = 0xe058; config_base = 0x98; break;
1559 default:
1560 /* Unknown number of ports, get out of here */
1561 return -EINVAL;
1562 }
1563
1564 if (idx < 4) {
1565 base = pci_resource_start(priv->dev, 3);
1566 ciobase = (int)(base + (0x8 * idx));
1567 }
1568
1569 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%lx ciobase=0x%lx config_base=0x%2x\n",
1570 __func__, idx, iobase, ciobase, config_base);
1571
1572 /* Enable UART I/O port */
1573 pci_write_config_byte(pdev, config_base + 0x00, 0x01);
1574
1575 /* Select 128-byte FIFO and 8x FIFO threshold */
1576 pci_write_config_byte(pdev, config_base + 0x01, 0x33);
1577
1578 /* LSB UART */
1579 pci_write_config_byte(pdev, config_base + 0x04, (u8)(iobase & 0xff));
1580
1581 /* MSB UART */
1582 pci_write_config_byte(pdev, config_base + 0x05, (u8)((iobase & 0xff00) >> 8));
1583
1584 /* irq number, this usually fails, but the spec says to do it anyway. */
1585 pci_write_config_byte(pdev, config_base + 0x06, pdev->irq);
1586
1587 port->port.iotype = UPIO_PORT;
1588 port->port.iobase = iobase;
1589 port->port.mapbase = 0;
1590 port->port.membase = NULL;
1591 port->port.regshift = 0;
1592
1593 return 0;
1594 }
1595
skip_tx_en_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1596 static int skip_tx_en_setup(struct serial_private *priv,
1597 const struct pciserial_board *board,
1598 struct uart_8250_port *port, int idx)
1599 {
1600 port->port.flags |= UPF_NO_TXEN_TEST;
1601 dev_dbg(&priv->dev->dev,
1602 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1603 priv->dev->vendor, priv->dev->device,
1604 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1605
1606 return pci_default_setup(priv, board, port, idx);
1607 }
1608
kt_handle_break(struct uart_port * p)1609 static void kt_handle_break(struct uart_port *p)
1610 {
1611 struct uart_8250_port *up = up_to_u8250p(p);
1612 /*
1613 * On receipt of a BI, serial device in Intel ME (Intel
1614 * management engine) needs to have its fifos cleared for sane
1615 * SOL (Serial Over Lan) output.
1616 */
1617 serial8250_clear_and_reinit_fifos(up);
1618 }
1619
kt_serial_in(struct uart_port * p,int offset)1620 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1621 {
1622 struct uart_8250_port *up = up_to_u8250p(p);
1623 unsigned int val;
1624
1625 /*
1626 * When the Intel ME (management engine) gets reset its serial
1627 * port registers could return 0 momentarily. Functions like
1628 * serial8250_console_write, read and save the IER, perform
1629 * some operation and then restore it. In order to avoid
1630 * setting IER register inadvertently to 0, if the value read
1631 * is 0, double check with ier value in uart_8250_port and use
1632 * that instead. up->ier should be the same value as what is
1633 * currently configured.
1634 */
1635 val = inb(p->iobase + offset);
1636 if (offset == UART_IER) {
1637 if (val == 0)
1638 val = up->ier;
1639 }
1640 return val;
1641 }
1642
kt_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1643 static int kt_serial_setup(struct serial_private *priv,
1644 const struct pciserial_board *board,
1645 struct uart_8250_port *port, int idx)
1646 {
1647 port->port.flags |= UPF_BUG_THRE;
1648 port->port.serial_in = kt_serial_in;
1649 port->port.handle_break = kt_handle_break;
1650 return skip_tx_en_setup(priv, board, port, idx);
1651 }
1652
pci_eg20t_init(struct pci_dev * dev)1653 static int pci_eg20t_init(struct pci_dev *dev)
1654 {
1655 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1656 return -ENODEV;
1657 #else
1658 return 0;
1659 #endif
1660 }
1661
1662 static int
pci_xr17c154_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1663 pci_xr17c154_setup(struct serial_private *priv,
1664 const struct pciserial_board *board,
1665 struct uart_8250_port *port, int idx)
1666 {
1667 port->port.flags |= UPF_EXAR_EFR;
1668 return pci_default_setup(priv, board, port, idx);
1669 }
1670
1671 static int
pci_xr17v35x_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1672 pci_xr17v35x_setup(struct serial_private *priv,
1673 const struct pciserial_board *board,
1674 struct uart_8250_port *port, int idx)
1675 {
1676 u8 __iomem *p;
1677
1678 p = pci_ioremap_bar(priv->dev, 0);
1679 if (p == NULL)
1680 return -ENOMEM;
1681
1682 port->port.flags |= UPF_EXAR_EFR;
1683
1684 /*
1685 * Setup Multipurpose Input/Output pins.
1686 */
1687 if (idx == 0) {
1688 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1689 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1690 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1691 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1692 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1693 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1694 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1695 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1696 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1697 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1698 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1699 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1700 }
1701 writeb(0x00, p + UART_EXAR_8XMODE);
1702 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1703 writeb(128, p + UART_EXAR_TXTRG);
1704 writeb(128, p + UART_EXAR_RXTRG);
1705 iounmap(p);
1706
1707 return pci_default_setup(priv, board, port, idx);
1708 }
1709
1710 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1711 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1712 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1713 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1714
1715 static int
pci_fastcom335_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1716 pci_fastcom335_setup(struct serial_private *priv,
1717 const struct pciserial_board *board,
1718 struct uart_8250_port *port, int idx)
1719 {
1720 u8 __iomem *p;
1721
1722 p = pci_ioremap_bar(priv->dev, 0);
1723 if (p == NULL)
1724 return -ENOMEM;
1725
1726 port->port.flags |= UPF_EXAR_EFR;
1727
1728 /*
1729 * Setup Multipurpose Input/Output pins.
1730 */
1731 if (idx == 0) {
1732 switch (priv->dev->device) {
1733 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1734 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1735 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1736 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1737 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1738 break;
1739 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1740 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1741 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1742 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1743 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1744 break;
1745 }
1746 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1747 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1748 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1749 }
1750 writeb(0x00, p + UART_EXAR_8XMODE);
1751 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1752 writeb(32, p + UART_EXAR_TXTRG);
1753 writeb(32, p + UART_EXAR_RXTRG);
1754 iounmap(p);
1755
1756 return pci_default_setup(priv, board, port, idx);
1757 }
1758
1759 static int
pci_wch_ch353_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1760 pci_wch_ch353_setup(struct serial_private *priv,
1761 const struct pciserial_board *board,
1762 struct uart_8250_port *port, int idx)
1763 {
1764 port->port.flags |= UPF_FIXED_TYPE;
1765 port->port.type = PORT_16550A;
1766 return pci_default_setup(priv, board, port, idx);
1767 }
1768
1769 static int
pci_wch_ch38x_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1770 pci_wch_ch38x_setup(struct serial_private *priv,
1771 const struct pciserial_board *board,
1772 struct uart_8250_port *port, int idx)
1773 {
1774 port->port.flags |= UPF_FIXED_TYPE;
1775 port->port.type = PORT_16850;
1776 return pci_default_setup(priv, board, port, idx);
1777 }
1778
1779 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1780 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1781 #define PCI_DEVICE_ID_OCTPRO 0x0001
1782 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1783 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1784 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1785 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1786 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1787 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1788 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1789 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1790 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1791 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1792 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1793 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1794 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1795 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1796 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1797 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1798 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1799 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1800 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1801 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1802 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1803 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1804 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1805 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1806 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1807 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1808 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1809 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1810 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1811 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1812 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1813 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1814 #define PCI_VENDOR_ID_WCH 0x4348
1815 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1816 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1817 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1818 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
1819 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1820 #define PCI_VENDOR_ID_AGESTAR 0x5372
1821 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1822 #define PCI_VENDOR_ID_ASIX 0x9710
1823 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1824 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1825 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1826 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1827 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1828 #define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936
1829
1830 #define PCI_VENDOR_ID_SUNIX 0x1fd4
1831 #define PCI_DEVICE_ID_SUNIX_1999 0x1999
1832
1833 #define PCIE_VENDOR_ID_WCH 0x1c00
1834 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
1835 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
1836 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
1837
1838 #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
1839 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
1840
1841 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1842 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1843 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1844
1845 /*
1846 * Master list of serial port init/setup/exit quirks.
1847 * This does not describe the general nature of the port.
1848 * (ie, baud base, number and location of ports, etc)
1849 *
1850 * This list is ordered alphabetically by vendor then device.
1851 * Specific entries must come before more generic entries.
1852 */
1853 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1854 /*
1855 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1856 */
1857 {
1858 .vendor = PCI_VENDOR_ID_AMCC,
1859 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1860 .subvendor = PCI_ANY_ID,
1861 .subdevice = PCI_ANY_ID,
1862 .setup = addidata_apci7800_setup,
1863 },
1864 /*
1865 * AFAVLAB cards - these may be called via parport_serial
1866 * It is not clear whether this applies to all products.
1867 */
1868 {
1869 .vendor = PCI_VENDOR_ID_AFAVLAB,
1870 .device = PCI_ANY_ID,
1871 .subvendor = PCI_ANY_ID,
1872 .subdevice = PCI_ANY_ID,
1873 .setup = afavlab_setup,
1874 },
1875 /*
1876 * HP Diva
1877 */
1878 {
1879 .vendor = PCI_VENDOR_ID_HP,
1880 .device = PCI_DEVICE_ID_HP_DIVA,
1881 .subvendor = PCI_ANY_ID,
1882 .subdevice = PCI_ANY_ID,
1883 .init = pci_hp_diva_init,
1884 .setup = pci_hp_diva_setup,
1885 },
1886 /*
1887 * Intel
1888 */
1889 {
1890 .vendor = PCI_VENDOR_ID_INTEL,
1891 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1892 .subvendor = 0xe4bf,
1893 .subdevice = PCI_ANY_ID,
1894 .init = pci_inteli960ni_init,
1895 .setup = pci_default_setup,
1896 },
1897 {
1898 .vendor = PCI_VENDOR_ID_INTEL,
1899 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1900 .subvendor = PCI_ANY_ID,
1901 .subdevice = PCI_ANY_ID,
1902 .setup = skip_tx_en_setup,
1903 },
1904 {
1905 .vendor = PCI_VENDOR_ID_INTEL,
1906 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1907 .subvendor = PCI_ANY_ID,
1908 .subdevice = PCI_ANY_ID,
1909 .setup = skip_tx_en_setup,
1910 },
1911 {
1912 .vendor = PCI_VENDOR_ID_INTEL,
1913 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1914 .subvendor = PCI_ANY_ID,
1915 .subdevice = PCI_ANY_ID,
1916 .setup = skip_tx_en_setup,
1917 },
1918 {
1919 .vendor = PCI_VENDOR_ID_INTEL,
1920 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1921 .subvendor = PCI_ANY_ID,
1922 .subdevice = PCI_ANY_ID,
1923 .setup = ce4100_serial_setup,
1924 },
1925 {
1926 .vendor = PCI_VENDOR_ID_INTEL,
1927 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1928 .subvendor = PCI_ANY_ID,
1929 .subdevice = PCI_ANY_ID,
1930 .setup = kt_serial_setup,
1931 },
1932 {
1933 .vendor = PCI_VENDOR_ID_INTEL,
1934 .device = PCI_DEVICE_ID_INTEL_BYT_UART1,
1935 .subvendor = PCI_ANY_ID,
1936 .subdevice = PCI_ANY_ID,
1937 .setup = byt_serial_setup,
1938 },
1939 {
1940 .vendor = PCI_VENDOR_ID_INTEL,
1941 .device = PCI_DEVICE_ID_INTEL_BYT_UART2,
1942 .subvendor = PCI_ANY_ID,
1943 .subdevice = PCI_ANY_ID,
1944 .setup = byt_serial_setup,
1945 },
1946 {
1947 .vendor = PCI_VENDOR_ID_INTEL,
1948 .device = PCI_DEVICE_ID_INTEL_QRK_UART,
1949 .subvendor = PCI_ANY_ID,
1950 .subdevice = PCI_ANY_ID,
1951 .setup = pci_default_setup,
1952 },
1953 {
1954 .vendor = PCI_VENDOR_ID_INTEL,
1955 .device = PCI_DEVICE_ID_INTEL_BSW_UART1,
1956 .subvendor = PCI_ANY_ID,
1957 .subdevice = PCI_ANY_ID,
1958 .setup = byt_serial_setup,
1959 },
1960 {
1961 .vendor = PCI_VENDOR_ID_INTEL,
1962 .device = PCI_DEVICE_ID_INTEL_BSW_UART2,
1963 .subvendor = PCI_ANY_ID,
1964 .subdevice = PCI_ANY_ID,
1965 .setup = byt_serial_setup,
1966 },
1967 {
1968 .vendor = PCI_VENDOR_ID_INTEL,
1969 .device = PCI_DEVICE_ID_INTEL_BDW_UART1,
1970 .subvendor = PCI_ANY_ID,
1971 .subdevice = PCI_ANY_ID,
1972 .setup = byt_serial_setup,
1973 },
1974 {
1975 .vendor = PCI_VENDOR_ID_INTEL,
1976 .device = PCI_DEVICE_ID_INTEL_BDW_UART2,
1977 .subvendor = PCI_ANY_ID,
1978 .subdevice = PCI_ANY_ID,
1979 .setup = byt_serial_setup,
1980 },
1981 /*
1982 * ITE
1983 */
1984 {
1985 .vendor = PCI_VENDOR_ID_ITE,
1986 .device = PCI_DEVICE_ID_ITE_8872,
1987 .subvendor = PCI_ANY_ID,
1988 .subdevice = PCI_ANY_ID,
1989 .init = pci_ite887x_init,
1990 .setup = pci_default_setup,
1991 .exit = pci_ite887x_exit,
1992 },
1993 /*
1994 * National Instruments
1995 */
1996 {
1997 .vendor = PCI_VENDOR_ID_NI,
1998 .device = PCI_DEVICE_ID_NI_PCI23216,
1999 .subvendor = PCI_ANY_ID,
2000 .subdevice = PCI_ANY_ID,
2001 .init = pci_ni8420_init,
2002 .setup = pci_default_setup,
2003 .exit = pci_ni8420_exit,
2004 },
2005 {
2006 .vendor = PCI_VENDOR_ID_NI,
2007 .device = PCI_DEVICE_ID_NI_PCI2328,
2008 .subvendor = PCI_ANY_ID,
2009 .subdevice = PCI_ANY_ID,
2010 .init = pci_ni8420_init,
2011 .setup = pci_default_setup,
2012 .exit = pci_ni8420_exit,
2013 },
2014 {
2015 .vendor = PCI_VENDOR_ID_NI,
2016 .device = PCI_DEVICE_ID_NI_PCI2324,
2017 .subvendor = PCI_ANY_ID,
2018 .subdevice = PCI_ANY_ID,
2019 .init = pci_ni8420_init,
2020 .setup = pci_default_setup,
2021 .exit = pci_ni8420_exit,
2022 },
2023 {
2024 .vendor = PCI_VENDOR_ID_NI,
2025 .device = PCI_DEVICE_ID_NI_PCI2322,
2026 .subvendor = PCI_ANY_ID,
2027 .subdevice = PCI_ANY_ID,
2028 .init = pci_ni8420_init,
2029 .setup = pci_default_setup,
2030 .exit = pci_ni8420_exit,
2031 },
2032 {
2033 .vendor = PCI_VENDOR_ID_NI,
2034 .device = PCI_DEVICE_ID_NI_PCI2324I,
2035 .subvendor = PCI_ANY_ID,
2036 .subdevice = PCI_ANY_ID,
2037 .init = pci_ni8420_init,
2038 .setup = pci_default_setup,
2039 .exit = pci_ni8420_exit,
2040 },
2041 {
2042 .vendor = PCI_VENDOR_ID_NI,
2043 .device = PCI_DEVICE_ID_NI_PCI2322I,
2044 .subvendor = PCI_ANY_ID,
2045 .subdevice = PCI_ANY_ID,
2046 .init = pci_ni8420_init,
2047 .setup = pci_default_setup,
2048 .exit = pci_ni8420_exit,
2049 },
2050 {
2051 .vendor = PCI_VENDOR_ID_NI,
2052 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2053 .subvendor = PCI_ANY_ID,
2054 .subdevice = PCI_ANY_ID,
2055 .init = pci_ni8420_init,
2056 .setup = pci_default_setup,
2057 .exit = pci_ni8420_exit,
2058 },
2059 {
2060 .vendor = PCI_VENDOR_ID_NI,
2061 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2062 .subvendor = PCI_ANY_ID,
2063 .subdevice = PCI_ANY_ID,
2064 .init = pci_ni8420_init,
2065 .setup = pci_default_setup,
2066 .exit = pci_ni8420_exit,
2067 },
2068 {
2069 .vendor = PCI_VENDOR_ID_NI,
2070 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2071 .subvendor = PCI_ANY_ID,
2072 .subdevice = PCI_ANY_ID,
2073 .init = pci_ni8420_init,
2074 .setup = pci_default_setup,
2075 .exit = pci_ni8420_exit,
2076 },
2077 {
2078 .vendor = PCI_VENDOR_ID_NI,
2079 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2080 .subvendor = PCI_ANY_ID,
2081 .subdevice = PCI_ANY_ID,
2082 .init = pci_ni8420_init,
2083 .setup = pci_default_setup,
2084 .exit = pci_ni8420_exit,
2085 },
2086 {
2087 .vendor = PCI_VENDOR_ID_NI,
2088 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2089 .subvendor = PCI_ANY_ID,
2090 .subdevice = PCI_ANY_ID,
2091 .init = pci_ni8420_init,
2092 .setup = pci_default_setup,
2093 .exit = pci_ni8420_exit,
2094 },
2095 {
2096 .vendor = PCI_VENDOR_ID_NI,
2097 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2098 .subvendor = PCI_ANY_ID,
2099 .subdevice = PCI_ANY_ID,
2100 .init = pci_ni8420_init,
2101 .setup = pci_default_setup,
2102 .exit = pci_ni8420_exit,
2103 },
2104 {
2105 .vendor = PCI_VENDOR_ID_NI,
2106 .device = PCI_ANY_ID,
2107 .subvendor = PCI_ANY_ID,
2108 .subdevice = PCI_ANY_ID,
2109 .init = pci_ni8430_init,
2110 .setup = pci_ni8430_setup,
2111 .exit = pci_ni8430_exit,
2112 },
2113 /* Quatech */
2114 {
2115 .vendor = PCI_VENDOR_ID_QUATECH,
2116 .device = PCI_ANY_ID,
2117 .subvendor = PCI_ANY_ID,
2118 .subdevice = PCI_ANY_ID,
2119 .init = pci_quatech_init,
2120 .setup = pci_quatech_setup,
2121 .exit = pci_quatech_exit,
2122 },
2123 /*
2124 * Panacom
2125 */
2126 {
2127 .vendor = PCI_VENDOR_ID_PANACOM,
2128 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2129 .subvendor = PCI_ANY_ID,
2130 .subdevice = PCI_ANY_ID,
2131 .init = pci_plx9050_init,
2132 .setup = pci_default_setup,
2133 .exit = pci_plx9050_exit,
2134 },
2135 {
2136 .vendor = PCI_VENDOR_ID_PANACOM,
2137 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2138 .subvendor = PCI_ANY_ID,
2139 .subdevice = PCI_ANY_ID,
2140 .init = pci_plx9050_init,
2141 .setup = pci_default_setup,
2142 .exit = pci_plx9050_exit,
2143 },
2144 /*
2145 * Pericom
2146 */
2147 {
2148 .vendor = 0x12d8,
2149 .device = 0x7952,
2150 .subvendor = PCI_ANY_ID,
2151 .subdevice = PCI_ANY_ID,
2152 .setup = pci_pericom_setup,
2153 },
2154 {
2155 .vendor = 0x12d8,
2156 .device = 0x7954,
2157 .subvendor = PCI_ANY_ID,
2158 .subdevice = PCI_ANY_ID,
2159 .setup = pci_pericom_setup,
2160 },
2161 {
2162 .vendor = 0x12d8,
2163 .device = 0x7958,
2164 .subvendor = PCI_ANY_ID,
2165 .subdevice = PCI_ANY_ID,
2166 .setup = pci_pericom_setup,
2167 },
2168
2169 /*
2170 * PLX
2171 */
2172 {
2173 .vendor = PCI_VENDOR_ID_PLX,
2174 .device = PCI_DEVICE_ID_PLX_9030,
2175 .subvendor = PCI_SUBVENDOR_ID_PERLE,
2176 .subdevice = PCI_ANY_ID,
2177 .setup = pci_default_setup,
2178 },
2179 {
2180 .vendor = PCI_VENDOR_ID_PLX,
2181 .device = PCI_DEVICE_ID_PLX_9050,
2182 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2183 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2184 .init = pci_plx9050_init,
2185 .setup = pci_default_setup,
2186 .exit = pci_plx9050_exit,
2187 },
2188 {
2189 .vendor = PCI_VENDOR_ID_PLX,
2190 .device = PCI_DEVICE_ID_PLX_9050,
2191 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2192 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2193 .init = pci_plx9050_init,
2194 .setup = pci_default_setup,
2195 .exit = pci_plx9050_exit,
2196 },
2197 {
2198 .vendor = PCI_VENDOR_ID_PLX,
2199 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2200 .subvendor = PCI_VENDOR_ID_PLX,
2201 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2202 .init = pci_plx9050_init,
2203 .setup = pci_default_setup,
2204 .exit = pci_plx9050_exit,
2205 },
2206 /*
2207 * SBS Technologies, Inc., PMC-OCTALPRO 232
2208 */
2209 {
2210 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2211 .device = PCI_DEVICE_ID_OCTPRO,
2212 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2213 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2214 .init = sbs_init,
2215 .setup = sbs_setup,
2216 .exit = sbs_exit,
2217 },
2218 /*
2219 * SBS Technologies, Inc., PMC-OCTALPRO 422
2220 */
2221 {
2222 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2223 .device = PCI_DEVICE_ID_OCTPRO,
2224 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2225 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2226 .init = sbs_init,
2227 .setup = sbs_setup,
2228 .exit = sbs_exit,
2229 },
2230 /*
2231 * SBS Technologies, Inc., P-Octal 232
2232 */
2233 {
2234 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2235 .device = PCI_DEVICE_ID_OCTPRO,
2236 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2237 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2238 .init = sbs_init,
2239 .setup = sbs_setup,
2240 .exit = sbs_exit,
2241 },
2242 /*
2243 * SBS Technologies, Inc., P-Octal 422
2244 */
2245 {
2246 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2247 .device = PCI_DEVICE_ID_OCTPRO,
2248 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2249 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2250 .init = sbs_init,
2251 .setup = sbs_setup,
2252 .exit = sbs_exit,
2253 },
2254 /*
2255 * SIIG cards - these may be called via parport_serial
2256 */
2257 {
2258 .vendor = PCI_VENDOR_ID_SIIG,
2259 .device = PCI_ANY_ID,
2260 .subvendor = PCI_ANY_ID,
2261 .subdevice = PCI_ANY_ID,
2262 .init = pci_siig_init,
2263 .setup = pci_siig_setup,
2264 },
2265 /*
2266 * Titan cards
2267 */
2268 {
2269 .vendor = PCI_VENDOR_ID_TITAN,
2270 .device = PCI_DEVICE_ID_TITAN_400L,
2271 .subvendor = PCI_ANY_ID,
2272 .subdevice = PCI_ANY_ID,
2273 .setup = titan_400l_800l_setup,
2274 },
2275 {
2276 .vendor = PCI_VENDOR_ID_TITAN,
2277 .device = PCI_DEVICE_ID_TITAN_800L,
2278 .subvendor = PCI_ANY_ID,
2279 .subdevice = PCI_ANY_ID,
2280 .setup = titan_400l_800l_setup,
2281 },
2282 /*
2283 * Timedia cards
2284 */
2285 {
2286 .vendor = PCI_VENDOR_ID_TIMEDIA,
2287 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2288 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2289 .subdevice = PCI_ANY_ID,
2290 .probe = pci_timedia_probe,
2291 .init = pci_timedia_init,
2292 .setup = pci_timedia_setup,
2293 },
2294 {
2295 .vendor = PCI_VENDOR_ID_TIMEDIA,
2296 .device = PCI_ANY_ID,
2297 .subvendor = PCI_ANY_ID,
2298 .subdevice = PCI_ANY_ID,
2299 .setup = pci_timedia_setup,
2300 },
2301 /*
2302 * SUNIX (Timedia) cards
2303 * Do not "probe" for these cards as there is at least one combination
2304 * card that should be handled by parport_pc that doesn't match the
2305 * rule in pci_timedia_probe.
2306 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2307 * There are some boards with part number SER5037AL that report
2308 * subdevice ID 0x0002.
2309 */
2310 {
2311 .vendor = PCI_VENDOR_ID_SUNIX,
2312 .device = PCI_DEVICE_ID_SUNIX_1999,
2313 .subvendor = PCI_VENDOR_ID_SUNIX,
2314 .subdevice = PCI_ANY_ID,
2315 .init = pci_timedia_init,
2316 .setup = pci_timedia_setup,
2317 },
2318 /*
2319 * Exar cards
2320 */
2321 {
2322 .vendor = PCI_VENDOR_ID_EXAR,
2323 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2324 .subvendor = PCI_ANY_ID,
2325 .subdevice = PCI_ANY_ID,
2326 .setup = pci_xr17c154_setup,
2327 },
2328 {
2329 .vendor = PCI_VENDOR_ID_EXAR,
2330 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2331 .subvendor = PCI_ANY_ID,
2332 .subdevice = PCI_ANY_ID,
2333 .setup = pci_xr17c154_setup,
2334 },
2335 {
2336 .vendor = PCI_VENDOR_ID_EXAR,
2337 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2338 .subvendor = PCI_ANY_ID,
2339 .subdevice = PCI_ANY_ID,
2340 .setup = pci_xr17c154_setup,
2341 },
2342 {
2343 .vendor = PCI_VENDOR_ID_EXAR,
2344 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2345 .subvendor = PCI_ANY_ID,
2346 .subdevice = PCI_ANY_ID,
2347 .setup = pci_xr17v35x_setup,
2348 },
2349 {
2350 .vendor = PCI_VENDOR_ID_EXAR,
2351 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2352 .subvendor = PCI_ANY_ID,
2353 .subdevice = PCI_ANY_ID,
2354 .setup = pci_xr17v35x_setup,
2355 },
2356 {
2357 .vendor = PCI_VENDOR_ID_EXAR,
2358 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2359 .subvendor = PCI_ANY_ID,
2360 .subdevice = PCI_ANY_ID,
2361 .setup = pci_xr17v35x_setup,
2362 },
2363 {
2364 .vendor = PCI_VENDOR_ID_EXAR,
2365 .device = PCI_DEVICE_ID_EXAR_XR17V4358,
2366 .subvendor = PCI_ANY_ID,
2367 .subdevice = PCI_ANY_ID,
2368 .setup = pci_xr17v35x_setup,
2369 },
2370 {
2371 .vendor = PCI_VENDOR_ID_EXAR,
2372 .device = PCI_DEVICE_ID_EXAR_XR17V8358,
2373 .subvendor = PCI_ANY_ID,
2374 .subdevice = PCI_ANY_ID,
2375 .setup = pci_xr17v35x_setup,
2376 },
2377 /*
2378 * Xircom cards
2379 */
2380 {
2381 .vendor = PCI_VENDOR_ID_XIRCOM,
2382 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2383 .subvendor = PCI_ANY_ID,
2384 .subdevice = PCI_ANY_ID,
2385 .init = pci_xircom_init,
2386 .setup = pci_default_setup,
2387 },
2388 /*
2389 * Netmos cards - these may be called via parport_serial
2390 */
2391 {
2392 .vendor = PCI_VENDOR_ID_NETMOS,
2393 .device = PCI_ANY_ID,
2394 .subvendor = PCI_ANY_ID,
2395 .subdevice = PCI_ANY_ID,
2396 .init = pci_netmos_init,
2397 .setup = pci_netmos_9900_setup,
2398 },
2399 /*
2400 * For Oxford Semiconductor Tornado based devices
2401 */
2402 {
2403 .vendor = PCI_VENDOR_ID_OXSEMI,
2404 .device = PCI_ANY_ID,
2405 .subvendor = PCI_ANY_ID,
2406 .subdevice = PCI_ANY_ID,
2407 .init = pci_oxsemi_tornado_init,
2408 .setup = pci_default_setup,
2409 },
2410 {
2411 .vendor = PCI_VENDOR_ID_MAINPINE,
2412 .device = PCI_ANY_ID,
2413 .subvendor = PCI_ANY_ID,
2414 .subdevice = PCI_ANY_ID,
2415 .init = pci_oxsemi_tornado_init,
2416 .setup = pci_default_setup,
2417 },
2418 {
2419 .vendor = PCI_VENDOR_ID_DIGI,
2420 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2421 .subvendor = PCI_SUBVENDOR_ID_IBM,
2422 .subdevice = PCI_ANY_ID,
2423 .init = pci_oxsemi_tornado_init,
2424 .setup = pci_default_setup,
2425 },
2426 {
2427 .vendor = PCI_VENDOR_ID_INTEL,
2428 .device = 0x8811,
2429 .subvendor = PCI_ANY_ID,
2430 .subdevice = PCI_ANY_ID,
2431 .init = pci_eg20t_init,
2432 .setup = pci_default_setup,
2433 },
2434 {
2435 .vendor = PCI_VENDOR_ID_INTEL,
2436 .device = 0x8812,
2437 .subvendor = PCI_ANY_ID,
2438 .subdevice = PCI_ANY_ID,
2439 .init = pci_eg20t_init,
2440 .setup = pci_default_setup,
2441 },
2442 {
2443 .vendor = PCI_VENDOR_ID_INTEL,
2444 .device = 0x8813,
2445 .subvendor = PCI_ANY_ID,
2446 .subdevice = PCI_ANY_ID,
2447 .init = pci_eg20t_init,
2448 .setup = pci_default_setup,
2449 },
2450 {
2451 .vendor = PCI_VENDOR_ID_INTEL,
2452 .device = 0x8814,
2453 .subvendor = PCI_ANY_ID,
2454 .subdevice = PCI_ANY_ID,
2455 .init = pci_eg20t_init,
2456 .setup = pci_default_setup,
2457 },
2458 {
2459 .vendor = 0x10DB,
2460 .device = 0x8027,
2461 .subvendor = PCI_ANY_ID,
2462 .subdevice = PCI_ANY_ID,
2463 .init = pci_eg20t_init,
2464 .setup = pci_default_setup,
2465 },
2466 {
2467 .vendor = 0x10DB,
2468 .device = 0x8028,
2469 .subvendor = PCI_ANY_ID,
2470 .subdevice = PCI_ANY_ID,
2471 .init = pci_eg20t_init,
2472 .setup = pci_default_setup,
2473 },
2474 {
2475 .vendor = 0x10DB,
2476 .device = 0x8029,
2477 .subvendor = PCI_ANY_ID,
2478 .subdevice = PCI_ANY_ID,
2479 .init = pci_eg20t_init,
2480 .setup = pci_default_setup,
2481 },
2482 {
2483 .vendor = 0x10DB,
2484 .device = 0x800C,
2485 .subvendor = PCI_ANY_ID,
2486 .subdevice = PCI_ANY_ID,
2487 .init = pci_eg20t_init,
2488 .setup = pci_default_setup,
2489 },
2490 {
2491 .vendor = 0x10DB,
2492 .device = 0x800D,
2493 .subvendor = PCI_ANY_ID,
2494 .subdevice = PCI_ANY_ID,
2495 .init = pci_eg20t_init,
2496 .setup = pci_default_setup,
2497 },
2498 /*
2499 * Cronyx Omega PCI (PLX-chip based)
2500 */
2501 {
2502 .vendor = PCI_VENDOR_ID_PLX,
2503 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2504 .subvendor = PCI_ANY_ID,
2505 .subdevice = PCI_ANY_ID,
2506 .setup = pci_omegapci_setup,
2507 },
2508 /* WCH CH353 1S1P card (16550 clone) */
2509 {
2510 .vendor = PCI_VENDOR_ID_WCH,
2511 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2512 .subvendor = PCI_ANY_ID,
2513 .subdevice = PCI_ANY_ID,
2514 .setup = pci_wch_ch353_setup,
2515 },
2516 /* WCH CH353 2S1P card (16550 clone) */
2517 {
2518 .vendor = PCI_VENDOR_ID_WCH,
2519 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2520 .subvendor = PCI_ANY_ID,
2521 .subdevice = PCI_ANY_ID,
2522 .setup = pci_wch_ch353_setup,
2523 },
2524 /* WCH CH353 4S card (16550 clone) */
2525 {
2526 .vendor = PCI_VENDOR_ID_WCH,
2527 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2528 .subvendor = PCI_ANY_ID,
2529 .subdevice = PCI_ANY_ID,
2530 .setup = pci_wch_ch353_setup,
2531 },
2532 /* WCH CH353 2S1PF card (16550 clone) */
2533 {
2534 .vendor = PCI_VENDOR_ID_WCH,
2535 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2536 .subvendor = PCI_ANY_ID,
2537 .subdevice = PCI_ANY_ID,
2538 .setup = pci_wch_ch353_setup,
2539 },
2540 /* WCH CH352 2S card (16550 clone) */
2541 {
2542 .vendor = PCI_VENDOR_ID_WCH,
2543 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2544 .subvendor = PCI_ANY_ID,
2545 .subdevice = PCI_ANY_ID,
2546 .setup = pci_wch_ch353_setup,
2547 },
2548 /* WCH CH382 2S card (16850 clone) */
2549 {
2550 .vendor = PCIE_VENDOR_ID_WCH,
2551 .device = PCIE_DEVICE_ID_WCH_CH382_2S,
2552 .subvendor = PCI_ANY_ID,
2553 .subdevice = PCI_ANY_ID,
2554 .setup = pci_wch_ch38x_setup,
2555 },
2556 /* WCH CH382 2S1P card (16850 clone) */
2557 {
2558 .vendor = PCIE_VENDOR_ID_WCH,
2559 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2560 .subvendor = PCI_ANY_ID,
2561 .subdevice = PCI_ANY_ID,
2562 .setup = pci_wch_ch38x_setup,
2563 },
2564 /* WCH CH384 4S card (16850 clone) */
2565 {
2566 .vendor = PCIE_VENDOR_ID_WCH,
2567 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2568 .subvendor = PCI_ANY_ID,
2569 .subdevice = PCI_ANY_ID,
2570 .setup = pci_wch_ch38x_setup,
2571 },
2572 /*
2573 * ASIX devices with FIFO bug
2574 */
2575 {
2576 .vendor = PCI_VENDOR_ID_ASIX,
2577 .device = PCI_ANY_ID,
2578 .subvendor = PCI_ANY_ID,
2579 .subdevice = PCI_ANY_ID,
2580 .setup = pci_asix_setup,
2581 },
2582 /*
2583 * Commtech, Inc. Fastcom adapters
2584 *
2585 */
2586 {
2587 .vendor = PCI_VENDOR_ID_COMMTECH,
2588 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2589 .subvendor = PCI_ANY_ID,
2590 .subdevice = PCI_ANY_ID,
2591 .setup = pci_fastcom335_setup,
2592 },
2593 {
2594 .vendor = PCI_VENDOR_ID_COMMTECH,
2595 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2596 .subvendor = PCI_ANY_ID,
2597 .subdevice = PCI_ANY_ID,
2598 .setup = pci_fastcom335_setup,
2599 },
2600 {
2601 .vendor = PCI_VENDOR_ID_COMMTECH,
2602 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2603 .subvendor = PCI_ANY_ID,
2604 .subdevice = PCI_ANY_ID,
2605 .setup = pci_fastcom335_setup,
2606 },
2607 {
2608 .vendor = PCI_VENDOR_ID_COMMTECH,
2609 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2610 .subvendor = PCI_ANY_ID,
2611 .subdevice = PCI_ANY_ID,
2612 .setup = pci_fastcom335_setup,
2613 },
2614 {
2615 .vendor = PCI_VENDOR_ID_COMMTECH,
2616 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2617 .subvendor = PCI_ANY_ID,
2618 .subdevice = PCI_ANY_ID,
2619 .setup = pci_xr17v35x_setup,
2620 },
2621 {
2622 .vendor = PCI_VENDOR_ID_COMMTECH,
2623 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2624 .subvendor = PCI_ANY_ID,
2625 .subdevice = PCI_ANY_ID,
2626 .setup = pci_xr17v35x_setup,
2627 },
2628 {
2629 .vendor = PCI_VENDOR_ID_COMMTECH,
2630 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2631 .subvendor = PCI_ANY_ID,
2632 .subdevice = PCI_ANY_ID,
2633 .setup = pci_xr17v35x_setup,
2634 },
2635 /*
2636 * Broadcom TruManage (NetXtreme)
2637 */
2638 {
2639 .vendor = PCI_VENDOR_ID_BROADCOM,
2640 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2641 .subvendor = PCI_ANY_ID,
2642 .subdevice = PCI_ANY_ID,
2643 .setup = pci_brcm_trumanage_setup,
2644 },
2645 {
2646 .vendor = 0x1c29,
2647 .device = 0x1104,
2648 .subvendor = PCI_ANY_ID,
2649 .subdevice = PCI_ANY_ID,
2650 .setup = pci_fintek_setup,
2651 },
2652 {
2653 .vendor = 0x1c29,
2654 .device = 0x1108,
2655 .subvendor = PCI_ANY_ID,
2656 .subdevice = PCI_ANY_ID,
2657 .setup = pci_fintek_setup,
2658 },
2659 {
2660 .vendor = 0x1c29,
2661 .device = 0x1112,
2662 .subvendor = PCI_ANY_ID,
2663 .subdevice = PCI_ANY_ID,
2664 .setup = pci_fintek_setup,
2665 },
2666
2667 /*
2668 * Default "match everything" terminator entry
2669 */
2670 {
2671 .vendor = PCI_ANY_ID,
2672 .device = PCI_ANY_ID,
2673 .subvendor = PCI_ANY_ID,
2674 .subdevice = PCI_ANY_ID,
2675 .setup = pci_default_setup,
2676 }
2677 };
2678
quirk_id_matches(u32 quirk_id,u32 dev_id)2679 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2680 {
2681 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2682 }
2683
find_quirk(struct pci_dev * dev)2684 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2685 {
2686 struct pci_serial_quirk *quirk;
2687
2688 for (quirk = pci_serial_quirks; ; quirk++)
2689 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2690 quirk_id_matches(quirk->device, dev->device) &&
2691 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2692 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2693 break;
2694 return quirk;
2695 }
2696
get_pci_irq(struct pci_dev * dev,const struct pciserial_board * board)2697 static inline int get_pci_irq(struct pci_dev *dev,
2698 const struct pciserial_board *board)
2699 {
2700 if (board->flags & FL_NOIRQ)
2701 return 0;
2702 else
2703 return dev->irq;
2704 }
2705
2706 /*
2707 * This is the configuration table for all of the PCI serial boards
2708 * which we support. It is directly indexed by the pci_board_num_t enum
2709 * value, which is encoded in the pci_device_id PCI probe table's
2710 * driver_data member.
2711 *
2712 * The makeup of these names are:
2713 * pbn_bn{_bt}_n_baud{_offsetinhex}
2714 *
2715 * bn = PCI BAR number
2716 * bt = Index using PCI BARs
2717 * n = number of serial ports
2718 * baud = baud rate
2719 * offsetinhex = offset for each sequential port (in hex)
2720 *
2721 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2722 *
2723 * Please note: in theory if n = 1, _bt infix should make no difference.
2724 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2725 */
2726 enum pci_board_num_t {
2727 pbn_default = 0,
2728
2729 pbn_b0_1_115200,
2730 pbn_b0_2_115200,
2731 pbn_b0_4_115200,
2732 pbn_b0_5_115200,
2733 pbn_b0_8_115200,
2734
2735 pbn_b0_1_921600,
2736 pbn_b0_2_921600,
2737 pbn_b0_4_921600,
2738
2739 pbn_b0_2_1130000,
2740
2741 pbn_b0_4_1152000,
2742
2743 pbn_b0_2_1152000_200,
2744 pbn_b0_4_1152000_200,
2745 pbn_b0_8_1152000_200,
2746
2747 pbn_b0_4_1250000,
2748
2749 pbn_b0_2_1843200,
2750 pbn_b0_4_1843200,
2751
2752 pbn_b0_2_1843200_200,
2753 pbn_b0_4_1843200_200,
2754 pbn_b0_8_1843200_200,
2755
2756 pbn_b0_1_4000000,
2757
2758 pbn_b0_bt_1_115200,
2759 pbn_b0_bt_2_115200,
2760 pbn_b0_bt_4_115200,
2761 pbn_b0_bt_8_115200,
2762
2763 pbn_b0_bt_1_460800,
2764 pbn_b0_bt_2_460800,
2765 pbn_b0_bt_4_460800,
2766
2767 pbn_b0_bt_1_921600,
2768 pbn_b0_bt_2_921600,
2769 pbn_b0_bt_4_921600,
2770 pbn_b0_bt_8_921600,
2771
2772 pbn_b1_1_115200,
2773 pbn_b1_2_115200,
2774 pbn_b1_4_115200,
2775 pbn_b1_8_115200,
2776 pbn_b1_16_115200,
2777
2778 pbn_b1_1_921600,
2779 pbn_b1_2_921600,
2780 pbn_b1_4_921600,
2781 pbn_b1_8_921600,
2782
2783 pbn_b1_2_1250000,
2784
2785 pbn_b1_bt_1_115200,
2786 pbn_b1_bt_2_115200,
2787 pbn_b1_bt_4_115200,
2788
2789 pbn_b1_bt_2_921600,
2790
2791 pbn_b1_1_1382400,
2792 pbn_b1_2_1382400,
2793 pbn_b1_4_1382400,
2794 pbn_b1_8_1382400,
2795
2796 pbn_b2_1_115200,
2797 pbn_b2_2_115200,
2798 pbn_b2_4_115200,
2799 pbn_b2_8_115200,
2800
2801 pbn_b2_1_460800,
2802 pbn_b2_4_460800,
2803 pbn_b2_8_460800,
2804 pbn_b2_16_460800,
2805
2806 pbn_b2_1_921600,
2807 pbn_b2_4_921600,
2808 pbn_b2_8_921600,
2809
2810 pbn_b2_8_1152000,
2811
2812 pbn_b2_bt_1_115200,
2813 pbn_b2_bt_2_115200,
2814 pbn_b2_bt_4_115200,
2815
2816 pbn_b2_bt_2_921600,
2817 pbn_b2_bt_4_921600,
2818
2819 pbn_b3_2_115200,
2820 pbn_b3_4_115200,
2821 pbn_b3_8_115200,
2822
2823 pbn_b4_bt_2_921600,
2824 pbn_b4_bt_4_921600,
2825 pbn_b4_bt_8_921600,
2826
2827 /*
2828 * Board-specific versions.
2829 */
2830 pbn_panacom,
2831 pbn_panacom2,
2832 pbn_panacom4,
2833 pbn_plx_romulus,
2834 pbn_oxsemi,
2835 pbn_oxsemi_1_4000000,
2836 pbn_oxsemi_2_4000000,
2837 pbn_oxsemi_4_4000000,
2838 pbn_oxsemi_8_4000000,
2839 pbn_intel_i960,
2840 pbn_sgi_ioc3,
2841 pbn_computone_4,
2842 pbn_computone_6,
2843 pbn_computone_8,
2844 pbn_sbsxrsio,
2845 pbn_exar_XR17C152,
2846 pbn_exar_XR17C154,
2847 pbn_exar_XR17C158,
2848 pbn_exar_XR17V352,
2849 pbn_exar_XR17V354,
2850 pbn_exar_XR17V358,
2851 pbn_exar_XR17V4358,
2852 pbn_exar_XR17V8358,
2853 pbn_exar_ibm_saturn,
2854 pbn_pasemi_1682M,
2855 pbn_ni8430_2,
2856 pbn_ni8430_4,
2857 pbn_ni8430_8,
2858 pbn_ni8430_16,
2859 pbn_ADDIDATA_PCIe_1_3906250,
2860 pbn_ADDIDATA_PCIe_2_3906250,
2861 pbn_ADDIDATA_PCIe_4_3906250,
2862 pbn_ADDIDATA_PCIe_8_3906250,
2863 pbn_ce4100_1_115200,
2864 pbn_byt,
2865 pbn_qrk,
2866 pbn_omegapci,
2867 pbn_NETMOS9900_2s_115200,
2868 pbn_brcm_trumanage,
2869 pbn_fintek_4,
2870 pbn_fintek_8,
2871 pbn_fintek_12,
2872 pbn_wch382_2,
2873 pbn_wch384_4,
2874 };
2875
2876 /*
2877 * uart_offset - the space between channels
2878 * reg_shift - describes how the UART registers are mapped
2879 * to PCI memory by the card.
2880 * For example IER register on SBS, Inc. PMC-OctPro is located at
2881 * offset 0x10 from the UART base, while UART_IER is defined as 1
2882 * in include/linux/serial_reg.h,
2883 * see first lines of serial_in() and serial_out() in 8250.c
2884 */
2885
2886 static struct pciserial_board pci_boards[] = {
2887 [pbn_default] = {
2888 .flags = FL_BASE0,
2889 .num_ports = 1,
2890 .base_baud = 115200,
2891 .uart_offset = 8,
2892 },
2893 [pbn_b0_1_115200] = {
2894 .flags = FL_BASE0,
2895 .num_ports = 1,
2896 .base_baud = 115200,
2897 .uart_offset = 8,
2898 },
2899 [pbn_b0_2_115200] = {
2900 .flags = FL_BASE0,
2901 .num_ports = 2,
2902 .base_baud = 115200,
2903 .uart_offset = 8,
2904 },
2905 [pbn_b0_4_115200] = {
2906 .flags = FL_BASE0,
2907 .num_ports = 4,
2908 .base_baud = 115200,
2909 .uart_offset = 8,
2910 },
2911 [pbn_b0_5_115200] = {
2912 .flags = FL_BASE0,
2913 .num_ports = 5,
2914 .base_baud = 115200,
2915 .uart_offset = 8,
2916 },
2917 [pbn_b0_8_115200] = {
2918 .flags = FL_BASE0,
2919 .num_ports = 8,
2920 .base_baud = 115200,
2921 .uart_offset = 8,
2922 },
2923 [pbn_b0_1_921600] = {
2924 .flags = FL_BASE0,
2925 .num_ports = 1,
2926 .base_baud = 921600,
2927 .uart_offset = 8,
2928 },
2929 [pbn_b0_2_921600] = {
2930 .flags = FL_BASE0,
2931 .num_ports = 2,
2932 .base_baud = 921600,
2933 .uart_offset = 8,
2934 },
2935 [pbn_b0_4_921600] = {
2936 .flags = FL_BASE0,
2937 .num_ports = 4,
2938 .base_baud = 921600,
2939 .uart_offset = 8,
2940 },
2941
2942 [pbn_b0_2_1130000] = {
2943 .flags = FL_BASE0,
2944 .num_ports = 2,
2945 .base_baud = 1130000,
2946 .uart_offset = 8,
2947 },
2948
2949 [pbn_b0_4_1152000] = {
2950 .flags = FL_BASE0,
2951 .num_ports = 4,
2952 .base_baud = 1152000,
2953 .uart_offset = 8,
2954 },
2955
2956 [pbn_b0_2_1152000_200] = {
2957 .flags = FL_BASE0,
2958 .num_ports = 2,
2959 .base_baud = 1152000,
2960 .uart_offset = 0x200,
2961 },
2962
2963 [pbn_b0_4_1152000_200] = {
2964 .flags = FL_BASE0,
2965 .num_ports = 4,
2966 .base_baud = 1152000,
2967 .uart_offset = 0x200,
2968 },
2969
2970 [pbn_b0_8_1152000_200] = {
2971 .flags = FL_BASE0,
2972 .num_ports = 8,
2973 .base_baud = 1152000,
2974 .uart_offset = 0x200,
2975 },
2976
2977 [pbn_b0_4_1250000] = {
2978 .flags = FL_BASE0,
2979 .num_ports = 4,
2980 .base_baud = 1250000,
2981 .uart_offset = 8,
2982 },
2983
2984 [pbn_b0_2_1843200] = {
2985 .flags = FL_BASE0,
2986 .num_ports = 2,
2987 .base_baud = 1843200,
2988 .uart_offset = 8,
2989 },
2990 [pbn_b0_4_1843200] = {
2991 .flags = FL_BASE0,
2992 .num_ports = 4,
2993 .base_baud = 1843200,
2994 .uart_offset = 8,
2995 },
2996
2997 [pbn_b0_2_1843200_200] = {
2998 .flags = FL_BASE0,
2999 .num_ports = 2,
3000 .base_baud = 1843200,
3001 .uart_offset = 0x200,
3002 },
3003 [pbn_b0_4_1843200_200] = {
3004 .flags = FL_BASE0,
3005 .num_ports = 4,
3006 .base_baud = 1843200,
3007 .uart_offset = 0x200,
3008 },
3009 [pbn_b0_8_1843200_200] = {
3010 .flags = FL_BASE0,
3011 .num_ports = 8,
3012 .base_baud = 1843200,
3013 .uart_offset = 0x200,
3014 },
3015 [pbn_b0_1_4000000] = {
3016 .flags = FL_BASE0,
3017 .num_ports = 1,
3018 .base_baud = 4000000,
3019 .uart_offset = 8,
3020 },
3021
3022 [pbn_b0_bt_1_115200] = {
3023 .flags = FL_BASE0|FL_BASE_BARS,
3024 .num_ports = 1,
3025 .base_baud = 115200,
3026 .uart_offset = 8,
3027 },
3028 [pbn_b0_bt_2_115200] = {
3029 .flags = FL_BASE0|FL_BASE_BARS,
3030 .num_ports = 2,
3031 .base_baud = 115200,
3032 .uart_offset = 8,
3033 },
3034 [pbn_b0_bt_4_115200] = {
3035 .flags = FL_BASE0|FL_BASE_BARS,
3036 .num_ports = 4,
3037 .base_baud = 115200,
3038 .uart_offset = 8,
3039 },
3040 [pbn_b0_bt_8_115200] = {
3041 .flags = FL_BASE0|FL_BASE_BARS,
3042 .num_ports = 8,
3043 .base_baud = 115200,
3044 .uart_offset = 8,
3045 },
3046
3047 [pbn_b0_bt_1_460800] = {
3048 .flags = FL_BASE0|FL_BASE_BARS,
3049 .num_ports = 1,
3050 .base_baud = 460800,
3051 .uart_offset = 8,
3052 },
3053 [pbn_b0_bt_2_460800] = {
3054 .flags = FL_BASE0|FL_BASE_BARS,
3055 .num_ports = 2,
3056 .base_baud = 460800,
3057 .uart_offset = 8,
3058 },
3059 [pbn_b0_bt_4_460800] = {
3060 .flags = FL_BASE0|FL_BASE_BARS,
3061 .num_ports = 4,
3062 .base_baud = 460800,
3063 .uart_offset = 8,
3064 },
3065
3066 [pbn_b0_bt_1_921600] = {
3067 .flags = FL_BASE0|FL_BASE_BARS,
3068 .num_ports = 1,
3069 .base_baud = 921600,
3070 .uart_offset = 8,
3071 },
3072 [pbn_b0_bt_2_921600] = {
3073 .flags = FL_BASE0|FL_BASE_BARS,
3074 .num_ports = 2,
3075 .base_baud = 921600,
3076 .uart_offset = 8,
3077 },
3078 [pbn_b0_bt_4_921600] = {
3079 .flags = FL_BASE0|FL_BASE_BARS,
3080 .num_ports = 4,
3081 .base_baud = 921600,
3082 .uart_offset = 8,
3083 },
3084 [pbn_b0_bt_8_921600] = {
3085 .flags = FL_BASE0|FL_BASE_BARS,
3086 .num_ports = 8,
3087 .base_baud = 921600,
3088 .uart_offset = 8,
3089 },
3090
3091 [pbn_b1_1_115200] = {
3092 .flags = FL_BASE1,
3093 .num_ports = 1,
3094 .base_baud = 115200,
3095 .uart_offset = 8,
3096 },
3097 [pbn_b1_2_115200] = {
3098 .flags = FL_BASE1,
3099 .num_ports = 2,
3100 .base_baud = 115200,
3101 .uart_offset = 8,
3102 },
3103 [pbn_b1_4_115200] = {
3104 .flags = FL_BASE1,
3105 .num_ports = 4,
3106 .base_baud = 115200,
3107 .uart_offset = 8,
3108 },
3109 [pbn_b1_8_115200] = {
3110 .flags = FL_BASE1,
3111 .num_ports = 8,
3112 .base_baud = 115200,
3113 .uart_offset = 8,
3114 },
3115 [pbn_b1_16_115200] = {
3116 .flags = FL_BASE1,
3117 .num_ports = 16,
3118 .base_baud = 115200,
3119 .uart_offset = 8,
3120 },
3121
3122 [pbn_b1_1_921600] = {
3123 .flags = FL_BASE1,
3124 .num_ports = 1,
3125 .base_baud = 921600,
3126 .uart_offset = 8,
3127 },
3128 [pbn_b1_2_921600] = {
3129 .flags = FL_BASE1,
3130 .num_ports = 2,
3131 .base_baud = 921600,
3132 .uart_offset = 8,
3133 },
3134 [pbn_b1_4_921600] = {
3135 .flags = FL_BASE1,
3136 .num_ports = 4,
3137 .base_baud = 921600,
3138 .uart_offset = 8,
3139 },
3140 [pbn_b1_8_921600] = {
3141 .flags = FL_BASE1,
3142 .num_ports = 8,
3143 .base_baud = 921600,
3144 .uart_offset = 8,
3145 },
3146 [pbn_b1_2_1250000] = {
3147 .flags = FL_BASE1,
3148 .num_ports = 2,
3149 .base_baud = 1250000,
3150 .uart_offset = 8,
3151 },
3152
3153 [pbn_b1_bt_1_115200] = {
3154 .flags = FL_BASE1|FL_BASE_BARS,
3155 .num_ports = 1,
3156 .base_baud = 115200,
3157 .uart_offset = 8,
3158 },
3159 [pbn_b1_bt_2_115200] = {
3160 .flags = FL_BASE1|FL_BASE_BARS,
3161 .num_ports = 2,
3162 .base_baud = 115200,
3163 .uart_offset = 8,
3164 },
3165 [pbn_b1_bt_4_115200] = {
3166 .flags = FL_BASE1|FL_BASE_BARS,
3167 .num_ports = 4,
3168 .base_baud = 115200,
3169 .uart_offset = 8,
3170 },
3171
3172 [pbn_b1_bt_2_921600] = {
3173 .flags = FL_BASE1|FL_BASE_BARS,
3174 .num_ports = 2,
3175 .base_baud = 921600,
3176 .uart_offset = 8,
3177 },
3178
3179 [pbn_b1_1_1382400] = {
3180 .flags = FL_BASE1,
3181 .num_ports = 1,
3182 .base_baud = 1382400,
3183 .uart_offset = 8,
3184 },
3185 [pbn_b1_2_1382400] = {
3186 .flags = FL_BASE1,
3187 .num_ports = 2,
3188 .base_baud = 1382400,
3189 .uart_offset = 8,
3190 },
3191 [pbn_b1_4_1382400] = {
3192 .flags = FL_BASE1,
3193 .num_ports = 4,
3194 .base_baud = 1382400,
3195 .uart_offset = 8,
3196 },
3197 [pbn_b1_8_1382400] = {
3198 .flags = FL_BASE1,
3199 .num_ports = 8,
3200 .base_baud = 1382400,
3201 .uart_offset = 8,
3202 },
3203
3204 [pbn_b2_1_115200] = {
3205 .flags = FL_BASE2,
3206 .num_ports = 1,
3207 .base_baud = 115200,
3208 .uart_offset = 8,
3209 },
3210 [pbn_b2_2_115200] = {
3211 .flags = FL_BASE2,
3212 .num_ports = 2,
3213 .base_baud = 115200,
3214 .uart_offset = 8,
3215 },
3216 [pbn_b2_4_115200] = {
3217 .flags = FL_BASE2,
3218 .num_ports = 4,
3219 .base_baud = 115200,
3220 .uart_offset = 8,
3221 },
3222 [pbn_b2_8_115200] = {
3223 .flags = FL_BASE2,
3224 .num_ports = 8,
3225 .base_baud = 115200,
3226 .uart_offset = 8,
3227 },
3228
3229 [pbn_b2_1_460800] = {
3230 .flags = FL_BASE2,
3231 .num_ports = 1,
3232 .base_baud = 460800,
3233 .uart_offset = 8,
3234 },
3235 [pbn_b2_4_460800] = {
3236 .flags = FL_BASE2,
3237 .num_ports = 4,
3238 .base_baud = 460800,
3239 .uart_offset = 8,
3240 },
3241 [pbn_b2_8_460800] = {
3242 .flags = FL_BASE2,
3243 .num_ports = 8,
3244 .base_baud = 460800,
3245 .uart_offset = 8,
3246 },
3247 [pbn_b2_16_460800] = {
3248 .flags = FL_BASE2,
3249 .num_ports = 16,
3250 .base_baud = 460800,
3251 .uart_offset = 8,
3252 },
3253
3254 [pbn_b2_1_921600] = {
3255 .flags = FL_BASE2,
3256 .num_ports = 1,
3257 .base_baud = 921600,
3258 .uart_offset = 8,
3259 },
3260 [pbn_b2_4_921600] = {
3261 .flags = FL_BASE2,
3262 .num_ports = 4,
3263 .base_baud = 921600,
3264 .uart_offset = 8,
3265 },
3266 [pbn_b2_8_921600] = {
3267 .flags = FL_BASE2,
3268 .num_ports = 8,
3269 .base_baud = 921600,
3270 .uart_offset = 8,
3271 },
3272
3273 [pbn_b2_8_1152000] = {
3274 .flags = FL_BASE2,
3275 .num_ports = 8,
3276 .base_baud = 1152000,
3277 .uart_offset = 8,
3278 },
3279
3280 [pbn_b2_bt_1_115200] = {
3281 .flags = FL_BASE2|FL_BASE_BARS,
3282 .num_ports = 1,
3283 .base_baud = 115200,
3284 .uart_offset = 8,
3285 },
3286 [pbn_b2_bt_2_115200] = {
3287 .flags = FL_BASE2|FL_BASE_BARS,
3288 .num_ports = 2,
3289 .base_baud = 115200,
3290 .uart_offset = 8,
3291 },
3292 [pbn_b2_bt_4_115200] = {
3293 .flags = FL_BASE2|FL_BASE_BARS,
3294 .num_ports = 4,
3295 .base_baud = 115200,
3296 .uart_offset = 8,
3297 },
3298
3299 [pbn_b2_bt_2_921600] = {
3300 .flags = FL_BASE2|FL_BASE_BARS,
3301 .num_ports = 2,
3302 .base_baud = 921600,
3303 .uart_offset = 8,
3304 },
3305 [pbn_b2_bt_4_921600] = {
3306 .flags = FL_BASE2|FL_BASE_BARS,
3307 .num_ports = 4,
3308 .base_baud = 921600,
3309 .uart_offset = 8,
3310 },
3311
3312 [pbn_b3_2_115200] = {
3313 .flags = FL_BASE3,
3314 .num_ports = 2,
3315 .base_baud = 115200,
3316 .uart_offset = 8,
3317 },
3318 [pbn_b3_4_115200] = {
3319 .flags = FL_BASE3,
3320 .num_ports = 4,
3321 .base_baud = 115200,
3322 .uart_offset = 8,
3323 },
3324 [pbn_b3_8_115200] = {
3325 .flags = FL_BASE3,
3326 .num_ports = 8,
3327 .base_baud = 115200,
3328 .uart_offset = 8,
3329 },
3330
3331 [pbn_b4_bt_2_921600] = {
3332 .flags = FL_BASE4,
3333 .num_ports = 2,
3334 .base_baud = 921600,
3335 .uart_offset = 8,
3336 },
3337 [pbn_b4_bt_4_921600] = {
3338 .flags = FL_BASE4,
3339 .num_ports = 4,
3340 .base_baud = 921600,
3341 .uart_offset = 8,
3342 },
3343 [pbn_b4_bt_8_921600] = {
3344 .flags = FL_BASE4,
3345 .num_ports = 8,
3346 .base_baud = 921600,
3347 .uart_offset = 8,
3348 },
3349
3350 /*
3351 * Entries following this are board-specific.
3352 */
3353
3354 /*
3355 * Panacom - IOMEM
3356 */
3357 [pbn_panacom] = {
3358 .flags = FL_BASE2,
3359 .num_ports = 2,
3360 .base_baud = 921600,
3361 .uart_offset = 0x400,
3362 .reg_shift = 7,
3363 },
3364 [pbn_panacom2] = {
3365 .flags = FL_BASE2|FL_BASE_BARS,
3366 .num_ports = 2,
3367 .base_baud = 921600,
3368 .uart_offset = 0x400,
3369 .reg_shift = 7,
3370 },
3371 [pbn_panacom4] = {
3372 .flags = FL_BASE2|FL_BASE_BARS,
3373 .num_ports = 4,
3374 .base_baud = 921600,
3375 .uart_offset = 0x400,
3376 .reg_shift = 7,
3377 },
3378
3379 /* I think this entry is broken - the first_offset looks wrong --rmk */
3380 [pbn_plx_romulus] = {
3381 .flags = FL_BASE2,
3382 .num_ports = 4,
3383 .base_baud = 921600,
3384 .uart_offset = 8 << 2,
3385 .reg_shift = 2,
3386 .first_offset = 0x03,
3387 },
3388
3389 /*
3390 * This board uses the size of PCI Base region 0 to
3391 * signal now many ports are available
3392 */
3393 [pbn_oxsemi] = {
3394 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3395 .num_ports = 32,
3396 .base_baud = 115200,
3397 .uart_offset = 8,
3398 },
3399 [pbn_oxsemi_1_4000000] = {
3400 .flags = FL_BASE0,
3401 .num_ports = 1,
3402 .base_baud = 4000000,
3403 .uart_offset = 0x200,
3404 .first_offset = 0x1000,
3405 },
3406 [pbn_oxsemi_2_4000000] = {
3407 .flags = FL_BASE0,
3408 .num_ports = 2,
3409 .base_baud = 4000000,
3410 .uart_offset = 0x200,
3411 .first_offset = 0x1000,
3412 },
3413 [pbn_oxsemi_4_4000000] = {
3414 .flags = FL_BASE0,
3415 .num_ports = 4,
3416 .base_baud = 4000000,
3417 .uart_offset = 0x200,
3418 .first_offset = 0x1000,
3419 },
3420 [pbn_oxsemi_8_4000000] = {
3421 .flags = FL_BASE0,
3422 .num_ports = 8,
3423 .base_baud = 4000000,
3424 .uart_offset = 0x200,
3425 .first_offset = 0x1000,
3426 },
3427
3428
3429 /*
3430 * EKF addition for i960 Boards form EKF with serial port.
3431 * Max 256 ports.
3432 */
3433 [pbn_intel_i960] = {
3434 .flags = FL_BASE0,
3435 .num_ports = 32,
3436 .base_baud = 921600,
3437 .uart_offset = 8 << 2,
3438 .reg_shift = 2,
3439 .first_offset = 0x10000,
3440 },
3441 [pbn_sgi_ioc3] = {
3442 .flags = FL_BASE0|FL_NOIRQ,
3443 .num_ports = 1,
3444 .base_baud = 458333,
3445 .uart_offset = 8,
3446 .reg_shift = 0,
3447 .first_offset = 0x20178,
3448 },
3449
3450 /*
3451 * Computone - uses IOMEM.
3452 */
3453 [pbn_computone_4] = {
3454 .flags = FL_BASE0,
3455 .num_ports = 4,
3456 .base_baud = 921600,
3457 .uart_offset = 0x40,
3458 .reg_shift = 2,
3459 .first_offset = 0x200,
3460 },
3461 [pbn_computone_6] = {
3462 .flags = FL_BASE0,
3463 .num_ports = 6,
3464 .base_baud = 921600,
3465 .uart_offset = 0x40,
3466 .reg_shift = 2,
3467 .first_offset = 0x200,
3468 },
3469 [pbn_computone_8] = {
3470 .flags = FL_BASE0,
3471 .num_ports = 8,
3472 .base_baud = 921600,
3473 .uart_offset = 0x40,
3474 .reg_shift = 2,
3475 .first_offset = 0x200,
3476 },
3477 [pbn_sbsxrsio] = {
3478 .flags = FL_BASE0,
3479 .num_ports = 8,
3480 .base_baud = 460800,
3481 .uart_offset = 256,
3482 .reg_shift = 4,
3483 },
3484 /*
3485 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3486 * Only basic 16550A support.
3487 * XR17C15[24] are not tested, but they should work.
3488 */
3489 [pbn_exar_XR17C152] = {
3490 .flags = FL_BASE0,
3491 .num_ports = 2,
3492 .base_baud = 921600,
3493 .uart_offset = 0x200,
3494 },
3495 [pbn_exar_XR17C154] = {
3496 .flags = FL_BASE0,
3497 .num_ports = 4,
3498 .base_baud = 921600,
3499 .uart_offset = 0x200,
3500 },
3501 [pbn_exar_XR17C158] = {
3502 .flags = FL_BASE0,
3503 .num_ports = 8,
3504 .base_baud = 921600,
3505 .uart_offset = 0x200,
3506 },
3507 [pbn_exar_XR17V352] = {
3508 .flags = FL_BASE0,
3509 .num_ports = 2,
3510 .base_baud = 7812500,
3511 .uart_offset = 0x400,
3512 .reg_shift = 0,
3513 .first_offset = 0,
3514 },
3515 [pbn_exar_XR17V354] = {
3516 .flags = FL_BASE0,
3517 .num_ports = 4,
3518 .base_baud = 7812500,
3519 .uart_offset = 0x400,
3520 .reg_shift = 0,
3521 .first_offset = 0,
3522 },
3523 [pbn_exar_XR17V358] = {
3524 .flags = FL_BASE0,
3525 .num_ports = 8,
3526 .base_baud = 7812500,
3527 .uart_offset = 0x400,
3528 .reg_shift = 0,
3529 .first_offset = 0,
3530 },
3531 [pbn_exar_XR17V4358] = {
3532 .flags = FL_BASE0,
3533 .num_ports = 12,
3534 .base_baud = 7812500,
3535 .uart_offset = 0x400,
3536 .reg_shift = 0,
3537 .first_offset = 0,
3538 },
3539 [pbn_exar_XR17V8358] = {
3540 .flags = FL_BASE0,
3541 .num_ports = 16,
3542 .base_baud = 7812500,
3543 .uart_offset = 0x400,
3544 .reg_shift = 0,
3545 .first_offset = 0,
3546 },
3547 [pbn_exar_ibm_saturn] = {
3548 .flags = FL_BASE0,
3549 .num_ports = 1,
3550 .base_baud = 921600,
3551 .uart_offset = 0x200,
3552 },
3553
3554 /*
3555 * PA Semi PWRficient PA6T-1682M on-chip UART
3556 */
3557 [pbn_pasemi_1682M] = {
3558 .flags = FL_BASE0,
3559 .num_ports = 1,
3560 .base_baud = 8333333,
3561 },
3562 /*
3563 * National Instruments 843x
3564 */
3565 [pbn_ni8430_16] = {
3566 .flags = FL_BASE0,
3567 .num_ports = 16,
3568 .base_baud = 3686400,
3569 .uart_offset = 0x10,
3570 .first_offset = 0x800,
3571 },
3572 [pbn_ni8430_8] = {
3573 .flags = FL_BASE0,
3574 .num_ports = 8,
3575 .base_baud = 3686400,
3576 .uart_offset = 0x10,
3577 .first_offset = 0x800,
3578 },
3579 [pbn_ni8430_4] = {
3580 .flags = FL_BASE0,
3581 .num_ports = 4,
3582 .base_baud = 3686400,
3583 .uart_offset = 0x10,
3584 .first_offset = 0x800,
3585 },
3586 [pbn_ni8430_2] = {
3587 .flags = FL_BASE0,
3588 .num_ports = 2,
3589 .base_baud = 3686400,
3590 .uart_offset = 0x10,
3591 .first_offset = 0x800,
3592 },
3593 /*
3594 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3595 */
3596 [pbn_ADDIDATA_PCIe_1_3906250] = {
3597 .flags = FL_BASE0,
3598 .num_ports = 1,
3599 .base_baud = 3906250,
3600 .uart_offset = 0x200,
3601 .first_offset = 0x1000,
3602 },
3603 [pbn_ADDIDATA_PCIe_2_3906250] = {
3604 .flags = FL_BASE0,
3605 .num_ports = 2,
3606 .base_baud = 3906250,
3607 .uart_offset = 0x200,
3608 .first_offset = 0x1000,
3609 },
3610 [pbn_ADDIDATA_PCIe_4_3906250] = {
3611 .flags = FL_BASE0,
3612 .num_ports = 4,
3613 .base_baud = 3906250,
3614 .uart_offset = 0x200,
3615 .first_offset = 0x1000,
3616 },
3617 [pbn_ADDIDATA_PCIe_8_3906250] = {
3618 .flags = FL_BASE0,
3619 .num_ports = 8,
3620 .base_baud = 3906250,
3621 .uart_offset = 0x200,
3622 .first_offset = 0x1000,
3623 },
3624 [pbn_ce4100_1_115200] = {
3625 .flags = FL_BASE_BARS,
3626 .num_ports = 2,
3627 .base_baud = 921600,
3628 .reg_shift = 2,
3629 },
3630 /*
3631 * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
3632 * but is overridden by byt_set_termios.
3633 */
3634 [pbn_byt] = {
3635 .flags = FL_BASE0,
3636 .num_ports = 1,
3637 .base_baud = 2764800,
3638 .uart_offset = 0x80,
3639 .reg_shift = 2,
3640 },
3641 [pbn_qrk] = {
3642 .flags = FL_BASE0,
3643 .num_ports = 1,
3644 .base_baud = 2764800,
3645 .reg_shift = 2,
3646 },
3647 [pbn_omegapci] = {
3648 .flags = FL_BASE0,
3649 .num_ports = 8,
3650 .base_baud = 115200,
3651 .uart_offset = 0x200,
3652 },
3653 [pbn_NETMOS9900_2s_115200] = {
3654 .flags = FL_BASE0,
3655 .num_ports = 2,
3656 .base_baud = 115200,
3657 },
3658 [pbn_brcm_trumanage] = {
3659 .flags = FL_BASE0,
3660 .num_ports = 1,
3661 .reg_shift = 2,
3662 .base_baud = 115200,
3663 },
3664 [pbn_fintek_4] = {
3665 .num_ports = 4,
3666 .uart_offset = 8,
3667 .base_baud = 115200,
3668 .first_offset = 0x40,
3669 },
3670 [pbn_fintek_8] = {
3671 .num_ports = 8,
3672 .uart_offset = 8,
3673 .base_baud = 115200,
3674 .first_offset = 0x40,
3675 },
3676 [pbn_fintek_12] = {
3677 .num_ports = 12,
3678 .uart_offset = 8,
3679 .base_baud = 115200,
3680 .first_offset = 0x40,
3681 },
3682 [pbn_wch382_2] = {
3683 .flags = FL_BASE0,
3684 .num_ports = 2,
3685 .base_baud = 115200,
3686 .uart_offset = 8,
3687 .first_offset = 0xC0,
3688 },
3689 [pbn_wch384_4] = {
3690 .flags = FL_BASE0,
3691 .num_ports = 4,
3692 .base_baud = 115200,
3693 .uart_offset = 8,
3694 .first_offset = 0xC0,
3695 },
3696 };
3697
3698 static const struct pci_device_id blacklist[] = {
3699 /* softmodems */
3700 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3701 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3702 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3703
3704 /* multi-io cards handled by parport_serial */
3705 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3706 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3707 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3708 { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
3709 };
3710
3711 /*
3712 * Given a complete unknown PCI device, try to use some heuristics to
3713 * guess what the configuration might be, based on the pitiful PCI
3714 * serial specs. Returns 0 on success, 1 on failure.
3715 */
3716 static int
serial_pci_guess_board(struct pci_dev * dev,struct pciserial_board * board)3717 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3718 {
3719 const struct pci_device_id *bldev;
3720 int num_iomem, num_port, first_port = -1, i;
3721
3722 /*
3723 * If it is not a communications device or the programming
3724 * interface is greater than 6, give up.
3725 *
3726 * (Should we try to make guesses for multiport serial devices
3727 * later?)
3728 */
3729 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3730 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3731 (dev->class & 0xff) > 6)
3732 return -ENODEV;
3733
3734 /*
3735 * Do not access blacklisted devices that are known not to
3736 * feature serial ports or are handled by other modules.
3737 */
3738 for (bldev = blacklist;
3739 bldev < blacklist + ARRAY_SIZE(blacklist);
3740 bldev++) {
3741 if (dev->vendor == bldev->vendor &&
3742 dev->device == bldev->device)
3743 return -ENODEV;
3744 }
3745
3746 num_iomem = num_port = 0;
3747 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3748 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3749 num_port++;
3750 if (first_port == -1)
3751 first_port = i;
3752 }
3753 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3754 num_iomem++;
3755 }
3756
3757 /*
3758 * If there is 1 or 0 iomem regions, and exactly one port,
3759 * use it. We guess the number of ports based on the IO
3760 * region size.
3761 */
3762 if (num_iomem <= 1 && num_port == 1) {
3763 board->flags = first_port;
3764 board->num_ports = pci_resource_len(dev, first_port) / 8;
3765 return 0;
3766 }
3767
3768 /*
3769 * Now guess if we've got a board which indexes by BARs.
3770 * Each IO BAR should be 8 bytes, and they should follow
3771 * consecutively.
3772 */
3773 first_port = -1;
3774 num_port = 0;
3775 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3776 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3777 pci_resource_len(dev, i) == 8 &&
3778 (first_port == -1 || (first_port + num_port) == i)) {
3779 num_port++;
3780 if (first_port == -1)
3781 first_port = i;
3782 }
3783 }
3784
3785 if (num_port > 1) {
3786 board->flags = first_port | FL_BASE_BARS;
3787 board->num_ports = num_port;
3788 return 0;
3789 }
3790
3791 return -ENODEV;
3792 }
3793
3794 static inline int
serial_pci_matches(const struct pciserial_board * board,const struct pciserial_board * guessed)3795 serial_pci_matches(const struct pciserial_board *board,
3796 const struct pciserial_board *guessed)
3797 {
3798 return
3799 board->num_ports == guessed->num_ports &&
3800 board->base_baud == guessed->base_baud &&
3801 board->uart_offset == guessed->uart_offset &&
3802 board->reg_shift == guessed->reg_shift &&
3803 board->first_offset == guessed->first_offset;
3804 }
3805
3806 struct serial_private *
pciserial_init_ports(struct pci_dev * dev,const struct pciserial_board * board)3807 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3808 {
3809 struct uart_8250_port uart;
3810 struct serial_private *priv;
3811 struct pci_serial_quirk *quirk;
3812 int rc, nr_ports, i;
3813
3814 nr_ports = board->num_ports;
3815
3816 /*
3817 * Find an init and setup quirks.
3818 */
3819 quirk = find_quirk(dev);
3820
3821 /*
3822 * Run the new-style initialization function.
3823 * The initialization function returns:
3824 * <0 - error
3825 * 0 - use board->num_ports
3826 * >0 - number of ports
3827 */
3828 if (quirk->init) {
3829 rc = quirk->init(dev);
3830 if (rc < 0) {
3831 priv = ERR_PTR(rc);
3832 goto err_out;
3833 }
3834 if (rc)
3835 nr_ports = rc;
3836 }
3837
3838 priv = kzalloc(sizeof(struct serial_private) +
3839 sizeof(unsigned int) * nr_ports,
3840 GFP_KERNEL);
3841 if (!priv) {
3842 priv = ERR_PTR(-ENOMEM);
3843 goto err_deinit;
3844 }
3845
3846 priv->dev = dev;
3847 priv->quirk = quirk;
3848
3849 memset(&uart, 0, sizeof(uart));
3850 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3851 uart.port.uartclk = board->base_baud * 16;
3852 uart.port.irq = get_pci_irq(dev, board);
3853 uart.port.dev = &dev->dev;
3854
3855 for (i = 0; i < nr_ports; i++) {
3856 if (quirk->setup(priv, board, &uart, i))
3857 break;
3858
3859 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3860 uart.port.iobase, uart.port.irq, uart.port.iotype);
3861
3862 priv->line[i] = serial8250_register_8250_port(&uart);
3863 if (priv->line[i] < 0) {
3864 dev_err(&dev->dev,
3865 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3866 uart.port.iobase, uart.port.irq,
3867 uart.port.iotype, priv->line[i]);
3868 break;
3869 }
3870 }
3871 priv->nr = i;
3872 priv->board = board;
3873 return priv;
3874
3875 err_deinit:
3876 if (quirk->exit)
3877 quirk->exit(dev);
3878 err_out:
3879 return priv;
3880 }
3881 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3882
pciserial_detach_ports(struct serial_private * priv)3883 void pciserial_detach_ports(struct serial_private *priv)
3884 {
3885 struct pci_serial_quirk *quirk;
3886 int i;
3887
3888 for (i = 0; i < priv->nr; i++)
3889 serial8250_unregister_port(priv->line[i]);
3890
3891 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3892 if (priv->remapped_bar[i])
3893 iounmap(priv->remapped_bar[i]);
3894 priv->remapped_bar[i] = NULL;
3895 }
3896
3897 /*
3898 * Find the exit quirks.
3899 */
3900 quirk = find_quirk(priv->dev);
3901 if (quirk->exit)
3902 quirk->exit(priv->dev);
3903 }
3904
pciserial_remove_ports(struct serial_private * priv)3905 void pciserial_remove_ports(struct serial_private *priv)
3906 {
3907 pciserial_detach_ports(priv);
3908 kfree(priv);
3909 }
3910 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3911
pciserial_suspend_ports(struct serial_private * priv)3912 void pciserial_suspend_ports(struct serial_private *priv)
3913 {
3914 int i;
3915
3916 for (i = 0; i < priv->nr; i++)
3917 if (priv->line[i] >= 0)
3918 serial8250_suspend_port(priv->line[i]);
3919
3920 /*
3921 * Ensure that every init quirk is properly torn down
3922 */
3923 if (priv->quirk->exit)
3924 priv->quirk->exit(priv->dev);
3925 }
3926 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3927
pciserial_resume_ports(struct serial_private * priv)3928 void pciserial_resume_ports(struct serial_private *priv)
3929 {
3930 int i;
3931
3932 /*
3933 * Ensure that the board is correctly configured.
3934 */
3935 if (priv->quirk->init)
3936 priv->quirk->init(priv->dev);
3937
3938 for (i = 0; i < priv->nr; i++)
3939 if (priv->line[i] >= 0)
3940 serial8250_resume_port(priv->line[i]);
3941 }
3942 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3943
3944 /*
3945 * Probe one serial board. Unfortunately, there is no rhyme nor reason
3946 * to the arrangement of serial ports on a PCI card.
3947 */
3948 static int
pciserial_init_one(struct pci_dev * dev,const struct pci_device_id * ent)3949 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3950 {
3951 struct pci_serial_quirk *quirk;
3952 struct serial_private *priv;
3953 const struct pciserial_board *board;
3954 struct pciserial_board tmp;
3955 int rc;
3956
3957 quirk = find_quirk(dev);
3958 if (quirk->probe) {
3959 rc = quirk->probe(dev);
3960 if (rc)
3961 return rc;
3962 }
3963
3964 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3965 dev_err(&dev->dev, "invalid driver_data: %ld\n",
3966 ent->driver_data);
3967 return -EINVAL;
3968 }
3969
3970 board = &pci_boards[ent->driver_data];
3971
3972 rc = pci_enable_device(dev);
3973 pci_save_state(dev);
3974 if (rc)
3975 return rc;
3976
3977 if (ent->driver_data == pbn_default) {
3978 /*
3979 * Use a copy of the pci_board entry for this;
3980 * avoid changing entries in the table.
3981 */
3982 memcpy(&tmp, board, sizeof(struct pciserial_board));
3983 board = &tmp;
3984
3985 /*
3986 * We matched one of our class entries. Try to
3987 * determine the parameters of this board.
3988 */
3989 rc = serial_pci_guess_board(dev, &tmp);
3990 if (rc)
3991 goto disable;
3992 } else {
3993 /*
3994 * We matched an explicit entry. If we are able to
3995 * detect this boards settings with our heuristic,
3996 * then we no longer need this entry.
3997 */
3998 memcpy(&tmp, &pci_boards[pbn_default],
3999 sizeof(struct pciserial_board));
4000 rc = serial_pci_guess_board(dev, &tmp);
4001 if (rc == 0 && serial_pci_matches(board, &tmp))
4002 moan_device("Redundant entry in serial pci_table.",
4003 dev);
4004 }
4005
4006 priv = pciserial_init_ports(dev, board);
4007 if (!IS_ERR(priv)) {
4008 pci_set_drvdata(dev, priv);
4009 return 0;
4010 }
4011
4012 rc = PTR_ERR(priv);
4013
4014 disable:
4015 pci_disable_device(dev);
4016 return rc;
4017 }
4018
pciserial_remove_one(struct pci_dev * dev)4019 static void pciserial_remove_one(struct pci_dev *dev)
4020 {
4021 struct serial_private *priv = pci_get_drvdata(dev);
4022
4023 pciserial_remove_ports(priv);
4024
4025 pci_disable_device(dev);
4026 }
4027
4028 #ifdef CONFIG_PM
pciserial_suspend_one(struct pci_dev * dev,pm_message_t state)4029 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
4030 {
4031 struct serial_private *priv = pci_get_drvdata(dev);
4032
4033 if (priv)
4034 pciserial_suspend_ports(priv);
4035
4036 pci_save_state(dev);
4037 pci_set_power_state(dev, pci_choose_state(dev, state));
4038 return 0;
4039 }
4040
pciserial_resume_one(struct pci_dev * dev)4041 static int pciserial_resume_one(struct pci_dev *dev)
4042 {
4043 int err;
4044 struct serial_private *priv = pci_get_drvdata(dev);
4045
4046 pci_set_power_state(dev, PCI_D0);
4047 pci_restore_state(dev);
4048
4049 if (priv) {
4050 /*
4051 * The device may have been disabled. Re-enable it.
4052 */
4053 err = pci_enable_device(dev);
4054 /* FIXME: We cannot simply error out here */
4055 if (err)
4056 dev_err(&dev->dev, "Unable to re-enable ports, trying to continue.\n");
4057 pciserial_resume_ports(priv);
4058 }
4059 return 0;
4060 }
4061 #endif
4062
4063 static struct pci_device_id serial_pci_tbl[] = {
4064 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4065 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4066 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4067 pbn_b2_8_921600 },
4068 /* Advantech also use 0x3618 and 0xf618 */
4069 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4070 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4071 pbn_b0_4_921600 },
4072 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4073 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4074 pbn_b0_4_921600 },
4075 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4076 PCI_SUBVENDOR_ID_CONNECT_TECH,
4077 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4078 pbn_b1_8_1382400 },
4079 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4080 PCI_SUBVENDOR_ID_CONNECT_TECH,
4081 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4082 pbn_b1_4_1382400 },
4083 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4084 PCI_SUBVENDOR_ID_CONNECT_TECH,
4085 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4086 pbn_b1_2_1382400 },
4087 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4088 PCI_SUBVENDOR_ID_CONNECT_TECH,
4089 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4090 pbn_b1_8_1382400 },
4091 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4092 PCI_SUBVENDOR_ID_CONNECT_TECH,
4093 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4094 pbn_b1_4_1382400 },
4095 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4096 PCI_SUBVENDOR_ID_CONNECT_TECH,
4097 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4098 pbn_b1_2_1382400 },
4099 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4100 PCI_SUBVENDOR_ID_CONNECT_TECH,
4101 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4102 pbn_b1_8_921600 },
4103 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4104 PCI_SUBVENDOR_ID_CONNECT_TECH,
4105 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4106 pbn_b1_8_921600 },
4107 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4108 PCI_SUBVENDOR_ID_CONNECT_TECH,
4109 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4110 pbn_b1_4_921600 },
4111 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4112 PCI_SUBVENDOR_ID_CONNECT_TECH,
4113 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4114 pbn_b1_4_921600 },
4115 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4116 PCI_SUBVENDOR_ID_CONNECT_TECH,
4117 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4118 pbn_b1_2_921600 },
4119 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4120 PCI_SUBVENDOR_ID_CONNECT_TECH,
4121 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4122 pbn_b1_8_921600 },
4123 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4124 PCI_SUBVENDOR_ID_CONNECT_TECH,
4125 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4126 pbn_b1_8_921600 },
4127 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4128 PCI_SUBVENDOR_ID_CONNECT_TECH,
4129 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4130 pbn_b1_4_921600 },
4131 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4132 PCI_SUBVENDOR_ID_CONNECT_TECH,
4133 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4134 pbn_b1_2_1250000 },
4135 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4136 PCI_SUBVENDOR_ID_CONNECT_TECH,
4137 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4138 pbn_b0_2_1843200 },
4139 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4140 PCI_SUBVENDOR_ID_CONNECT_TECH,
4141 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4142 pbn_b0_4_1843200 },
4143 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4144 PCI_VENDOR_ID_AFAVLAB,
4145 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4146 pbn_b0_4_1152000 },
4147 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4148 PCI_SUBVENDOR_ID_CONNECT_TECH,
4149 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4150 pbn_b0_2_1843200_200 },
4151 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4152 PCI_SUBVENDOR_ID_CONNECT_TECH,
4153 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4154 pbn_b0_4_1843200_200 },
4155 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4156 PCI_SUBVENDOR_ID_CONNECT_TECH,
4157 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4158 pbn_b0_8_1843200_200 },
4159 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4160 PCI_SUBVENDOR_ID_CONNECT_TECH,
4161 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4162 pbn_b0_2_1843200_200 },
4163 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4164 PCI_SUBVENDOR_ID_CONNECT_TECH,
4165 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4166 pbn_b0_4_1843200_200 },
4167 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4168 PCI_SUBVENDOR_ID_CONNECT_TECH,
4169 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4170 pbn_b0_8_1843200_200 },
4171 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4172 PCI_SUBVENDOR_ID_CONNECT_TECH,
4173 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4174 pbn_b0_2_1843200_200 },
4175 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4176 PCI_SUBVENDOR_ID_CONNECT_TECH,
4177 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4178 pbn_b0_4_1843200_200 },
4179 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4180 PCI_SUBVENDOR_ID_CONNECT_TECH,
4181 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4182 pbn_b0_8_1843200_200 },
4183 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4184 PCI_SUBVENDOR_ID_CONNECT_TECH,
4185 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4186 pbn_b0_2_1843200_200 },
4187 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4188 PCI_SUBVENDOR_ID_CONNECT_TECH,
4189 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4190 pbn_b0_4_1843200_200 },
4191 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4192 PCI_SUBVENDOR_ID_CONNECT_TECH,
4193 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4194 pbn_b0_8_1843200_200 },
4195 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4196 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4197 0, 0, pbn_exar_ibm_saturn },
4198
4199 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4200 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4201 pbn_b2_bt_1_115200 },
4202 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4203 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4204 pbn_b2_bt_2_115200 },
4205 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4206 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4207 pbn_b2_bt_4_115200 },
4208 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4209 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4210 pbn_b2_bt_2_115200 },
4211 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4212 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4213 pbn_b2_bt_4_115200 },
4214 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4215 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4216 pbn_b2_8_115200 },
4217 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4218 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4219 pbn_b2_8_460800 },
4220 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4221 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4222 pbn_b2_8_115200 },
4223
4224 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4225 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4226 pbn_b2_bt_2_115200 },
4227 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4228 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4229 pbn_b2_bt_2_921600 },
4230 /*
4231 * VScom SPCOM800, from sl@s.pl
4232 */
4233 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4234 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4235 pbn_b2_8_921600 },
4236 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4237 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4238 pbn_b2_4_921600 },
4239 /* Unknown card - subdevice 0x1584 */
4240 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4241 PCI_VENDOR_ID_PLX,
4242 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4243 pbn_b2_4_115200 },
4244 /* Unknown card - subdevice 0x1588 */
4245 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4246 PCI_VENDOR_ID_PLX,
4247 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4248 pbn_b2_8_115200 },
4249 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4250 PCI_SUBVENDOR_ID_KEYSPAN,
4251 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4252 pbn_panacom },
4253 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4254 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4255 pbn_panacom4 },
4256 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4257 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4258 pbn_panacom2 },
4259 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4260 PCI_VENDOR_ID_ESDGMBH,
4261 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4262 pbn_b2_4_115200 },
4263 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4264 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4265 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4266 pbn_b2_4_460800 },
4267 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4268 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4269 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4270 pbn_b2_8_460800 },
4271 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4272 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4273 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4274 pbn_b2_16_460800 },
4275 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4276 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4277 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4278 pbn_b2_16_460800 },
4279 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4280 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4281 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4282 pbn_b2_4_460800 },
4283 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4284 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4285 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4286 pbn_b2_8_460800 },
4287 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4288 PCI_SUBVENDOR_ID_EXSYS,
4289 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4290 pbn_b2_4_115200 },
4291 /*
4292 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4293 * (Exoray@isys.ca)
4294 */
4295 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4296 0x10b5, 0x106a, 0, 0,
4297 pbn_plx_romulus },
4298 /*
4299 * Quatech cards. These actually have configurable clocks but for
4300 * now we just use the default.
4301 *
4302 * 100 series are RS232, 200 series RS422,
4303 */
4304 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4305 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4306 pbn_b1_4_115200 },
4307 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4308 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4309 pbn_b1_2_115200 },
4310 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4311 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4312 pbn_b2_2_115200 },
4313 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4314 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4315 pbn_b1_2_115200 },
4316 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4317 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4318 pbn_b2_2_115200 },
4319 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4320 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4321 pbn_b1_4_115200 },
4322 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4323 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4324 pbn_b1_8_115200 },
4325 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4326 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4327 pbn_b1_8_115200 },
4328 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4329 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4330 pbn_b1_4_115200 },
4331 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4332 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4333 pbn_b1_2_115200 },
4334 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4335 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4336 pbn_b1_4_115200 },
4337 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4338 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4339 pbn_b1_2_115200 },
4340 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4341 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4342 pbn_b2_4_115200 },
4343 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4344 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4345 pbn_b2_2_115200 },
4346 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4347 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4348 pbn_b2_1_115200 },
4349 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4350 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4351 pbn_b2_4_115200 },
4352 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4353 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4354 pbn_b2_2_115200 },
4355 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4356 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4357 pbn_b2_1_115200 },
4358 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4359 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4360 pbn_b0_8_115200 },
4361
4362 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4363 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4364 0, 0,
4365 pbn_b0_4_921600 },
4366 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4367 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4368 0, 0,
4369 pbn_b0_4_1152000 },
4370 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4371 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4372 pbn_b0_bt_2_921600 },
4373
4374 /*
4375 * The below card is a little controversial since it is the
4376 * subject of a PCI vendor/device ID clash. (See
4377 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4378 * For now just used the hex ID 0x950a.
4379 */
4380 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4381 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4382 0, 0, pbn_b0_2_115200 },
4383 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4384 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4385 0, 0, pbn_b0_2_115200 },
4386 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4387 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4388 pbn_b0_2_1130000 },
4389 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4390 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4391 pbn_b0_1_921600 },
4392 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4393 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4394 pbn_b0_4_115200 },
4395 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4396 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4397 pbn_b0_bt_2_921600 },
4398 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4399 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4400 pbn_b2_8_1152000 },
4401
4402 /*
4403 * Oxford Semiconductor Inc. Tornado PCI express device range.
4404 */
4405 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4406 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4407 pbn_b0_1_4000000 },
4408 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4409 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4410 pbn_b0_1_4000000 },
4411 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4412 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4413 pbn_oxsemi_1_4000000 },
4414 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4415 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4416 pbn_oxsemi_1_4000000 },
4417 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4418 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4419 pbn_b0_1_4000000 },
4420 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4421 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4422 pbn_b0_1_4000000 },
4423 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4424 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4425 pbn_oxsemi_1_4000000 },
4426 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4427 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4428 pbn_oxsemi_1_4000000 },
4429 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4430 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4431 pbn_b0_1_4000000 },
4432 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4433 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4434 pbn_b0_1_4000000 },
4435 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4436 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4437 pbn_b0_1_4000000 },
4438 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4439 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4440 pbn_b0_1_4000000 },
4441 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4442 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4443 pbn_oxsemi_2_4000000 },
4444 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4445 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4446 pbn_oxsemi_2_4000000 },
4447 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4448 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4449 pbn_oxsemi_4_4000000 },
4450 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4451 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4452 pbn_oxsemi_4_4000000 },
4453 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4454 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4455 pbn_oxsemi_8_4000000 },
4456 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4457 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4458 pbn_oxsemi_8_4000000 },
4459 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4460 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4461 pbn_oxsemi_1_4000000 },
4462 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4463 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4464 pbn_oxsemi_1_4000000 },
4465 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4466 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4467 pbn_oxsemi_1_4000000 },
4468 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4469 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4470 pbn_oxsemi_1_4000000 },
4471 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4472 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4473 pbn_oxsemi_1_4000000 },
4474 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4475 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4476 pbn_oxsemi_1_4000000 },
4477 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4478 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4479 pbn_oxsemi_1_4000000 },
4480 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4481 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4482 pbn_oxsemi_1_4000000 },
4483 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4484 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4485 pbn_oxsemi_1_4000000 },
4486 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4487 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4488 pbn_oxsemi_1_4000000 },
4489 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4490 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4491 pbn_oxsemi_1_4000000 },
4492 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4493 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4494 pbn_oxsemi_1_4000000 },
4495 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4496 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4497 pbn_oxsemi_1_4000000 },
4498 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4499 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4500 pbn_oxsemi_1_4000000 },
4501 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4502 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4503 pbn_oxsemi_1_4000000 },
4504 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4505 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4506 pbn_oxsemi_1_4000000 },
4507 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4508 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4509 pbn_oxsemi_1_4000000 },
4510 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4511 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4512 pbn_oxsemi_1_4000000 },
4513 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4514 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4515 pbn_oxsemi_1_4000000 },
4516 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4517 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4518 pbn_oxsemi_1_4000000 },
4519 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4520 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4521 pbn_oxsemi_1_4000000 },
4522 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4523 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4524 pbn_oxsemi_1_4000000 },
4525 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4526 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4527 pbn_oxsemi_1_4000000 },
4528 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4529 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4530 pbn_oxsemi_1_4000000 },
4531 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4532 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4533 pbn_oxsemi_1_4000000 },
4534 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4535 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4536 pbn_oxsemi_1_4000000 },
4537 /*
4538 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4539 */
4540 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4541 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4542 pbn_oxsemi_1_4000000 },
4543 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4544 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4545 pbn_oxsemi_2_4000000 },
4546 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4547 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4548 pbn_oxsemi_4_4000000 },
4549 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4550 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4551 pbn_oxsemi_8_4000000 },
4552
4553 /*
4554 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4555 */
4556 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4557 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4558 pbn_oxsemi_2_4000000 },
4559
4560 /*
4561 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4562 * from skokodyn@yahoo.com
4563 */
4564 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4565 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4566 pbn_sbsxrsio },
4567 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4568 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4569 pbn_sbsxrsio },
4570 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4571 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4572 pbn_sbsxrsio },
4573 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4574 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4575 pbn_sbsxrsio },
4576
4577 /*
4578 * Digitan DS560-558, from jimd@esoft.com
4579 */
4580 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4581 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4582 pbn_b1_1_115200 },
4583
4584 /*
4585 * Titan Electronic cards
4586 * The 400L and 800L have a custom setup quirk.
4587 */
4588 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4589 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4590 pbn_b0_1_921600 },
4591 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4592 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4593 pbn_b0_2_921600 },
4594 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4595 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4596 pbn_b0_4_921600 },
4597 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4598 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4599 pbn_b0_4_921600 },
4600 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4601 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4602 pbn_b1_1_921600 },
4603 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4604 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4605 pbn_b1_bt_2_921600 },
4606 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4607 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4608 pbn_b0_bt_4_921600 },
4609 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4610 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4611 pbn_b0_bt_8_921600 },
4612 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4613 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4614 pbn_b4_bt_2_921600 },
4615 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4616 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4617 pbn_b4_bt_4_921600 },
4618 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4619 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4620 pbn_b4_bt_8_921600 },
4621 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4622 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4623 pbn_b0_4_921600 },
4624 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4625 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4626 pbn_b0_4_921600 },
4627 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4628 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4629 pbn_b0_4_921600 },
4630 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4631 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4632 pbn_oxsemi_1_4000000 },
4633 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4634 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4635 pbn_oxsemi_2_4000000 },
4636 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4637 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4638 pbn_oxsemi_4_4000000 },
4639 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4640 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4641 pbn_oxsemi_8_4000000 },
4642 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4643 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4644 pbn_oxsemi_2_4000000 },
4645 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4646 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4647 pbn_oxsemi_2_4000000 },
4648 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4649 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4650 pbn_b0_bt_2_921600 },
4651 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4652 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4653 pbn_b0_4_921600 },
4654 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4655 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4656 pbn_b0_4_921600 },
4657 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4658 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4659 pbn_b0_4_921600 },
4660 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4661 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4662 pbn_b0_4_921600 },
4663
4664 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4665 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4666 pbn_b2_1_460800 },
4667 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4668 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4669 pbn_b2_1_460800 },
4670 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4671 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4672 pbn_b2_1_460800 },
4673 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4674 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4675 pbn_b2_bt_2_921600 },
4676 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4677 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4678 pbn_b2_bt_2_921600 },
4679 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4680 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4681 pbn_b2_bt_2_921600 },
4682 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4683 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4684 pbn_b2_bt_4_921600 },
4685 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4686 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4687 pbn_b2_bt_4_921600 },
4688 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4689 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4690 pbn_b2_bt_4_921600 },
4691 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4692 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4693 pbn_b0_1_921600 },
4694 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4695 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4696 pbn_b0_1_921600 },
4697 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4698 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4699 pbn_b0_1_921600 },
4700 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4701 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4702 pbn_b0_bt_2_921600 },
4703 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4704 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4705 pbn_b0_bt_2_921600 },
4706 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4707 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4708 pbn_b0_bt_2_921600 },
4709 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4710 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4711 pbn_b0_bt_4_921600 },
4712 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4713 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4714 pbn_b0_bt_4_921600 },
4715 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4716 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4717 pbn_b0_bt_4_921600 },
4718 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4719 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4720 pbn_b0_bt_8_921600 },
4721 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4722 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4723 pbn_b0_bt_8_921600 },
4724 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4725 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4726 pbn_b0_bt_8_921600 },
4727
4728 /*
4729 * Computone devices submitted by Doug McNash dmcnash@computone.com
4730 */
4731 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4732 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4733 0, 0, pbn_computone_4 },
4734 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4735 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4736 0, 0, pbn_computone_8 },
4737 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4738 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4739 0, 0, pbn_computone_6 },
4740
4741 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4742 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4743 pbn_oxsemi },
4744 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4745 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4746 pbn_b0_bt_1_921600 },
4747
4748 /*
4749 * SUNIX (TIMEDIA)
4750 */
4751 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4752 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4753 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4754 pbn_b0_bt_1_921600 },
4755
4756 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4757 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4758 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4759 pbn_b0_bt_1_921600 },
4760
4761 /*
4762 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4763 */
4764 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4765 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4766 pbn_b0_bt_8_115200 },
4767 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4768 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4769 pbn_b0_bt_8_115200 },
4770
4771 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4772 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4773 pbn_b0_bt_2_115200 },
4774 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4775 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4776 pbn_b0_bt_2_115200 },
4777 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4778 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4779 pbn_b0_bt_2_115200 },
4780 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4781 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4782 pbn_b0_bt_2_115200 },
4783 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4784 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4785 pbn_b0_bt_2_115200 },
4786 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4787 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4788 pbn_b0_bt_4_460800 },
4789 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4790 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4791 pbn_b0_bt_4_460800 },
4792 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4793 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4794 pbn_b0_bt_2_460800 },
4795 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4796 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4797 pbn_b0_bt_2_460800 },
4798 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4799 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4800 pbn_b0_bt_2_460800 },
4801 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4802 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4803 pbn_b0_bt_1_115200 },
4804 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4805 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4806 pbn_b0_bt_1_460800 },
4807
4808 /*
4809 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4810 * Cards are identified by their subsystem vendor IDs, which
4811 * (in hex) match the model number.
4812 *
4813 * Note that JC140x are RS422/485 cards which require ox950
4814 * ACR = 0x10, and as such are not currently fully supported.
4815 */
4816 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4817 0x1204, 0x0004, 0, 0,
4818 pbn_b0_4_921600 },
4819 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4820 0x1208, 0x0004, 0, 0,
4821 pbn_b0_4_921600 },
4822 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4823 0x1402, 0x0002, 0, 0,
4824 pbn_b0_2_921600 }, */
4825 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4826 0x1404, 0x0004, 0, 0,
4827 pbn_b0_4_921600 }, */
4828 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4829 0x1208, 0x0004, 0, 0,
4830 pbn_b0_4_921600 },
4831
4832 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4833 0x1204, 0x0004, 0, 0,
4834 pbn_b0_4_921600 },
4835 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4836 0x1208, 0x0004, 0, 0,
4837 pbn_b0_4_921600 },
4838 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4839 0x1208, 0x0004, 0, 0,
4840 pbn_b0_4_921600 },
4841 /*
4842 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4843 */
4844 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4845 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4846 pbn_b1_1_1382400 },
4847
4848 /*
4849 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4850 */
4851 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4852 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4853 pbn_b1_1_1382400 },
4854
4855 /*
4856 * RAStel 2 port modem, gerg@moreton.com.au
4857 */
4858 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4859 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4860 pbn_b2_bt_2_115200 },
4861
4862 /*
4863 * EKF addition for i960 Boards form EKF with serial port
4864 */
4865 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4866 0xE4BF, PCI_ANY_ID, 0, 0,
4867 pbn_intel_i960 },
4868
4869 /*
4870 * Xircom Cardbus/Ethernet combos
4871 */
4872 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4873 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4874 pbn_b0_1_115200 },
4875 /*
4876 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4877 */
4878 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4879 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4880 pbn_b0_1_115200 },
4881
4882 /*
4883 * Untested PCI modems, sent in from various folks...
4884 */
4885
4886 /*
4887 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4888 */
4889 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4890 0x1048, 0x1500, 0, 0,
4891 pbn_b1_1_115200 },
4892
4893 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4894 0xFF00, 0, 0, 0,
4895 pbn_sgi_ioc3 },
4896
4897 /*
4898 * HP Diva card
4899 */
4900 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4901 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4902 pbn_b1_1_115200 },
4903 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4904 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4905 pbn_b0_5_115200 },
4906 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4907 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4908 pbn_b2_1_115200 },
4909
4910 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4911 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4912 pbn_b3_2_115200 },
4913 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4914 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4915 pbn_b3_4_115200 },
4916 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4917 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4918 pbn_b3_8_115200 },
4919
4920 /*
4921 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
4922 */
4923 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4924 PCI_ANY_ID, PCI_ANY_ID,
4925 0,
4926 0, pbn_exar_XR17C152 },
4927 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4928 PCI_ANY_ID, PCI_ANY_ID,
4929 0,
4930 0, pbn_exar_XR17C154 },
4931 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4932 PCI_ANY_ID, PCI_ANY_ID,
4933 0,
4934 0, pbn_exar_XR17C158 },
4935 /*
4936 * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs
4937 */
4938 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
4939 PCI_ANY_ID, PCI_ANY_ID,
4940 0,
4941 0, pbn_exar_XR17V352 },
4942 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
4943 PCI_ANY_ID, PCI_ANY_ID,
4944 0,
4945 0, pbn_exar_XR17V354 },
4946 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
4947 PCI_ANY_ID, PCI_ANY_ID,
4948 0,
4949 0, pbn_exar_XR17V358 },
4950 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V4358,
4951 PCI_ANY_ID, PCI_ANY_ID,
4952 0,
4953 0, pbn_exar_XR17V4358 },
4954 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358,
4955 PCI_ANY_ID, PCI_ANY_ID,
4956 0,
4957 0, pbn_exar_XR17V8358 },
4958 /*
4959 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4960 */
4961 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4962 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4963 pbn_b0_1_115200 },
4964 /*
4965 * ITE
4966 */
4967 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4968 PCI_ANY_ID, PCI_ANY_ID,
4969 0, 0,
4970 pbn_b1_bt_1_115200 },
4971
4972 /*
4973 * IntaShield IS-200
4974 */
4975 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4976 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
4977 pbn_b2_2_115200 },
4978 /*
4979 * IntaShield IS-400
4980 */
4981 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4982 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
4983 pbn_b2_4_115200 },
4984 /*
4985 * Perle PCI-RAS cards
4986 */
4987 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4988 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4989 0, 0, pbn_b2_4_921600 },
4990 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4991 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4992 0, 0, pbn_b2_8_921600 },
4993
4994 /*
4995 * Mainpine series cards: Fairly standard layout but fools
4996 * parts of the autodetect in some cases and uses otherwise
4997 * unmatched communications subclasses in the PCI Express case
4998 */
4999
5000 { /* RockForceDUO */
5001 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5002 PCI_VENDOR_ID_MAINPINE, 0x0200,
5003 0, 0, pbn_b0_2_115200 },
5004 { /* RockForceQUATRO */
5005 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5006 PCI_VENDOR_ID_MAINPINE, 0x0300,
5007 0, 0, pbn_b0_4_115200 },
5008 { /* RockForceDUO+ */
5009 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5010 PCI_VENDOR_ID_MAINPINE, 0x0400,
5011 0, 0, pbn_b0_2_115200 },
5012 { /* RockForceQUATRO+ */
5013 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5014 PCI_VENDOR_ID_MAINPINE, 0x0500,
5015 0, 0, pbn_b0_4_115200 },
5016 { /* RockForce+ */
5017 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5018 PCI_VENDOR_ID_MAINPINE, 0x0600,
5019 0, 0, pbn_b0_2_115200 },
5020 { /* RockForce+ */
5021 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5022 PCI_VENDOR_ID_MAINPINE, 0x0700,
5023 0, 0, pbn_b0_4_115200 },
5024 { /* RockForceOCTO+ */
5025 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5026 PCI_VENDOR_ID_MAINPINE, 0x0800,
5027 0, 0, pbn_b0_8_115200 },
5028 { /* RockForceDUO+ */
5029 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5030 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5031 0, 0, pbn_b0_2_115200 },
5032 { /* RockForceQUARTRO+ */
5033 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5034 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5035 0, 0, pbn_b0_4_115200 },
5036 { /* RockForceOCTO+ */
5037 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5038 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5039 0, 0, pbn_b0_8_115200 },
5040 { /* RockForceD1 */
5041 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5042 PCI_VENDOR_ID_MAINPINE, 0x2000,
5043 0, 0, pbn_b0_1_115200 },
5044 { /* RockForceF1 */
5045 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5046 PCI_VENDOR_ID_MAINPINE, 0x2100,
5047 0, 0, pbn_b0_1_115200 },
5048 { /* RockForceD2 */
5049 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5050 PCI_VENDOR_ID_MAINPINE, 0x2200,
5051 0, 0, pbn_b0_2_115200 },
5052 { /* RockForceF2 */
5053 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5054 PCI_VENDOR_ID_MAINPINE, 0x2300,
5055 0, 0, pbn_b0_2_115200 },
5056 { /* RockForceD4 */
5057 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5058 PCI_VENDOR_ID_MAINPINE, 0x2400,
5059 0, 0, pbn_b0_4_115200 },
5060 { /* RockForceF4 */
5061 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5062 PCI_VENDOR_ID_MAINPINE, 0x2500,
5063 0, 0, pbn_b0_4_115200 },
5064 { /* RockForceD8 */
5065 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5066 PCI_VENDOR_ID_MAINPINE, 0x2600,
5067 0, 0, pbn_b0_8_115200 },
5068 { /* RockForceF8 */
5069 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5070 PCI_VENDOR_ID_MAINPINE, 0x2700,
5071 0, 0, pbn_b0_8_115200 },
5072 { /* IQ Express D1 */
5073 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5074 PCI_VENDOR_ID_MAINPINE, 0x3000,
5075 0, 0, pbn_b0_1_115200 },
5076 { /* IQ Express F1 */
5077 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5078 PCI_VENDOR_ID_MAINPINE, 0x3100,
5079 0, 0, pbn_b0_1_115200 },
5080 { /* IQ Express D2 */
5081 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5082 PCI_VENDOR_ID_MAINPINE, 0x3200,
5083 0, 0, pbn_b0_2_115200 },
5084 { /* IQ Express F2 */
5085 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5086 PCI_VENDOR_ID_MAINPINE, 0x3300,
5087 0, 0, pbn_b0_2_115200 },
5088 { /* IQ Express D4 */
5089 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5090 PCI_VENDOR_ID_MAINPINE, 0x3400,
5091 0, 0, pbn_b0_4_115200 },
5092 { /* IQ Express F4 */
5093 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5094 PCI_VENDOR_ID_MAINPINE, 0x3500,
5095 0, 0, pbn_b0_4_115200 },
5096 { /* IQ Express D8 */
5097 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5098 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5099 0, 0, pbn_b0_8_115200 },
5100 { /* IQ Express F8 */
5101 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5102 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5103 0, 0, pbn_b0_8_115200 },
5104
5105
5106 /*
5107 * PA Semi PA6T-1682M on-chip UART
5108 */
5109 { PCI_VENDOR_ID_PASEMI, 0xa004,
5110 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5111 pbn_pasemi_1682M },
5112
5113 /*
5114 * National Instruments
5115 */
5116 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5117 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5118 pbn_b1_16_115200 },
5119 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5120 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5121 pbn_b1_8_115200 },
5122 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5123 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5124 pbn_b1_bt_4_115200 },
5125 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5126 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5127 pbn_b1_bt_2_115200 },
5128 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5129 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5130 pbn_b1_bt_4_115200 },
5131 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5132 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5133 pbn_b1_bt_2_115200 },
5134 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5135 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5136 pbn_b1_16_115200 },
5137 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5138 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5139 pbn_b1_8_115200 },
5140 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5141 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5142 pbn_b1_bt_4_115200 },
5143 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5144 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5145 pbn_b1_bt_2_115200 },
5146 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5147 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5148 pbn_b1_bt_4_115200 },
5149 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5150 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5151 pbn_b1_bt_2_115200 },
5152 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5153 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5154 pbn_ni8430_2 },
5155 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5156 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5157 pbn_ni8430_2 },
5158 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5159 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5160 pbn_ni8430_4 },
5161 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5162 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5163 pbn_ni8430_4 },
5164 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5165 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5166 pbn_ni8430_8 },
5167 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5168 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5169 pbn_ni8430_8 },
5170 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5171 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5172 pbn_ni8430_16 },
5173 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5174 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5175 pbn_ni8430_16 },
5176 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5177 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5178 pbn_ni8430_2 },
5179 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5180 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5181 pbn_ni8430_2 },
5182 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5183 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5184 pbn_ni8430_4 },
5185 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5186 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5187 pbn_ni8430_4 },
5188
5189 /*
5190 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5191 */
5192 { PCI_VENDOR_ID_ADDIDATA,
5193 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5194 PCI_ANY_ID,
5195 PCI_ANY_ID,
5196 0,
5197 0,
5198 pbn_b0_4_115200 },
5199
5200 { PCI_VENDOR_ID_ADDIDATA,
5201 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5202 PCI_ANY_ID,
5203 PCI_ANY_ID,
5204 0,
5205 0,
5206 pbn_b0_2_115200 },
5207
5208 { PCI_VENDOR_ID_ADDIDATA,
5209 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5210 PCI_ANY_ID,
5211 PCI_ANY_ID,
5212 0,
5213 0,
5214 pbn_b0_1_115200 },
5215
5216 { PCI_VENDOR_ID_AMCC,
5217 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5218 PCI_ANY_ID,
5219 PCI_ANY_ID,
5220 0,
5221 0,
5222 pbn_b1_8_115200 },
5223
5224 { PCI_VENDOR_ID_ADDIDATA,
5225 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5226 PCI_ANY_ID,
5227 PCI_ANY_ID,
5228 0,
5229 0,
5230 pbn_b0_4_115200 },
5231
5232 { PCI_VENDOR_ID_ADDIDATA,
5233 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5234 PCI_ANY_ID,
5235 PCI_ANY_ID,
5236 0,
5237 0,
5238 pbn_b0_2_115200 },
5239
5240 { PCI_VENDOR_ID_ADDIDATA,
5241 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5242 PCI_ANY_ID,
5243 PCI_ANY_ID,
5244 0,
5245 0,
5246 pbn_b0_1_115200 },
5247
5248 { PCI_VENDOR_ID_ADDIDATA,
5249 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5250 PCI_ANY_ID,
5251 PCI_ANY_ID,
5252 0,
5253 0,
5254 pbn_b0_4_115200 },
5255
5256 { PCI_VENDOR_ID_ADDIDATA,
5257 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5258 PCI_ANY_ID,
5259 PCI_ANY_ID,
5260 0,
5261 0,
5262 pbn_b0_2_115200 },
5263
5264 { PCI_VENDOR_ID_ADDIDATA,
5265 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5266 PCI_ANY_ID,
5267 PCI_ANY_ID,
5268 0,
5269 0,
5270 pbn_b0_1_115200 },
5271
5272 { PCI_VENDOR_ID_ADDIDATA,
5273 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5274 PCI_ANY_ID,
5275 PCI_ANY_ID,
5276 0,
5277 0,
5278 pbn_b0_8_115200 },
5279
5280 { PCI_VENDOR_ID_ADDIDATA,
5281 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5282 PCI_ANY_ID,
5283 PCI_ANY_ID,
5284 0,
5285 0,
5286 pbn_ADDIDATA_PCIe_4_3906250 },
5287
5288 { PCI_VENDOR_ID_ADDIDATA,
5289 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5290 PCI_ANY_ID,
5291 PCI_ANY_ID,
5292 0,
5293 0,
5294 pbn_ADDIDATA_PCIe_2_3906250 },
5295
5296 { PCI_VENDOR_ID_ADDIDATA,
5297 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5298 PCI_ANY_ID,
5299 PCI_ANY_ID,
5300 0,
5301 0,
5302 pbn_ADDIDATA_PCIe_1_3906250 },
5303
5304 { PCI_VENDOR_ID_ADDIDATA,
5305 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5306 PCI_ANY_ID,
5307 PCI_ANY_ID,
5308 0,
5309 0,
5310 pbn_ADDIDATA_PCIe_8_3906250 },
5311
5312 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5313 PCI_VENDOR_ID_IBM, 0x0299,
5314 0, 0, pbn_b0_bt_2_115200 },
5315
5316 /*
5317 * other NetMos 9835 devices are most likely handled by the
5318 * parport_serial driver, check drivers/parport/parport_serial.c
5319 * before adding them here.
5320 */
5321
5322 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5323 0xA000, 0x1000,
5324 0, 0, pbn_b0_1_115200 },
5325
5326 /* the 9901 is a rebranded 9912 */
5327 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5328 0xA000, 0x1000,
5329 0, 0, pbn_b0_1_115200 },
5330
5331 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5332 0xA000, 0x1000,
5333 0, 0, pbn_b0_1_115200 },
5334
5335 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5336 0xA000, 0x1000,
5337 0, 0, pbn_b0_1_115200 },
5338
5339 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5340 0xA000, 0x1000,
5341 0, 0, pbn_b0_1_115200 },
5342
5343 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5344 0xA000, 0x3002,
5345 0, 0, pbn_NETMOS9900_2s_115200 },
5346
5347 /*
5348 * Best Connectivity and Rosewill PCI Multi I/O cards
5349 */
5350
5351 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5352 0xA000, 0x1000,
5353 0, 0, pbn_b0_1_115200 },
5354
5355 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5356 0xA000, 0x3002,
5357 0, 0, pbn_b0_bt_2_115200 },
5358
5359 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5360 0xA000, 0x3004,
5361 0, 0, pbn_b0_bt_4_115200 },
5362 /* Intel CE4100 */
5363 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5364 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5365 pbn_ce4100_1_115200 },
5366 /* Intel BayTrail */
5367 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5368 PCI_ANY_ID, PCI_ANY_ID,
5369 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5370 pbn_byt },
5371 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5372 PCI_ANY_ID, PCI_ANY_ID,
5373 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5374 pbn_byt },
5375 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1,
5376 PCI_ANY_ID, PCI_ANY_ID,
5377 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5378 pbn_byt },
5379 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2,
5380 PCI_ANY_ID, PCI_ANY_ID,
5381 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5382 pbn_byt },
5383
5384 /* Intel Broadwell */
5385 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART1,
5386 PCI_ANY_ID, PCI_ANY_ID,
5387 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5388 pbn_byt },
5389 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART2,
5390 PCI_ANY_ID, PCI_ANY_ID,
5391 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5392 pbn_byt },
5393
5394 /*
5395 * Intel Quark x1000
5396 */
5397 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
5398 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5399 pbn_qrk },
5400 /*
5401 * Cronyx Omega PCI
5402 */
5403 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5404 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5405 pbn_omegapci },
5406
5407 /*
5408 * Broadcom TruManage
5409 */
5410 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5411 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5412 pbn_brcm_trumanage },
5413
5414 /*
5415 * AgeStar as-prs2-009
5416 */
5417 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5418 PCI_ANY_ID, PCI_ANY_ID,
5419 0, 0, pbn_b0_bt_2_115200 },
5420
5421 /*
5422 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5423 * so not listed here.
5424 */
5425 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5426 PCI_ANY_ID, PCI_ANY_ID,
5427 0, 0, pbn_b0_bt_4_115200 },
5428
5429 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5430 PCI_ANY_ID, PCI_ANY_ID,
5431 0, 0, pbn_b0_bt_2_115200 },
5432
5433 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH352_2S,
5434 PCI_ANY_ID, PCI_ANY_ID,
5435 0, 0, pbn_b0_bt_2_115200 },
5436
5437 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5438 PCI_ANY_ID, PCI_ANY_ID,
5439 0, 0, pbn_wch382_2 },
5440
5441 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5442 PCI_ANY_ID, PCI_ANY_ID,
5443 0, 0, pbn_wch384_4 },
5444
5445 /*
5446 * Commtech, Inc. Fastcom adapters
5447 */
5448 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5449 PCI_ANY_ID, PCI_ANY_ID,
5450 0,
5451 0, pbn_b0_2_1152000_200 },
5452 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5453 PCI_ANY_ID, PCI_ANY_ID,
5454 0,
5455 0, pbn_b0_4_1152000_200 },
5456 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5457 PCI_ANY_ID, PCI_ANY_ID,
5458 0,
5459 0, pbn_b0_4_1152000_200 },
5460 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5461 PCI_ANY_ID, PCI_ANY_ID,
5462 0,
5463 0, pbn_b0_8_1152000_200 },
5464 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5465 PCI_ANY_ID, PCI_ANY_ID,
5466 0,
5467 0, pbn_exar_XR17V352 },
5468 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5469 PCI_ANY_ID, PCI_ANY_ID,
5470 0,
5471 0, pbn_exar_XR17V354 },
5472 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5473 PCI_ANY_ID, PCI_ANY_ID,
5474 0,
5475 0, pbn_exar_XR17V358 },
5476
5477 /* Fintek PCI serial cards */
5478 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5479 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5480 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5481
5482 /* MKS Tenta SCOM-080x serial cards */
5483 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
5484 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
5485
5486 /* Amazon PCI serial device */
5487 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
5488
5489 /*
5490 * These entries match devices with class COMMUNICATION_SERIAL,
5491 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5492 */
5493 { PCI_ANY_ID, PCI_ANY_ID,
5494 PCI_ANY_ID, PCI_ANY_ID,
5495 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5496 0xffff00, pbn_default },
5497 { PCI_ANY_ID, PCI_ANY_ID,
5498 PCI_ANY_ID, PCI_ANY_ID,
5499 PCI_CLASS_COMMUNICATION_MODEM << 8,
5500 0xffff00, pbn_default },
5501 { PCI_ANY_ID, PCI_ANY_ID,
5502 PCI_ANY_ID, PCI_ANY_ID,
5503 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5504 0xffff00, pbn_default },
5505 { 0, }
5506 };
5507
serial8250_io_error_detected(struct pci_dev * dev,pci_channel_state_t state)5508 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5509 pci_channel_state_t state)
5510 {
5511 struct serial_private *priv = pci_get_drvdata(dev);
5512
5513 if (state == pci_channel_io_perm_failure)
5514 return PCI_ERS_RESULT_DISCONNECT;
5515
5516 if (priv)
5517 pciserial_detach_ports(priv);
5518
5519 pci_disable_device(dev);
5520
5521 return PCI_ERS_RESULT_NEED_RESET;
5522 }
5523
serial8250_io_slot_reset(struct pci_dev * dev)5524 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5525 {
5526 int rc;
5527
5528 rc = pci_enable_device(dev);
5529
5530 if (rc)
5531 return PCI_ERS_RESULT_DISCONNECT;
5532
5533 pci_restore_state(dev);
5534 pci_save_state(dev);
5535
5536 return PCI_ERS_RESULT_RECOVERED;
5537 }
5538
serial8250_io_resume(struct pci_dev * dev)5539 static void serial8250_io_resume(struct pci_dev *dev)
5540 {
5541 struct serial_private *priv = pci_get_drvdata(dev);
5542 const struct pciserial_board *board;
5543
5544 if (!priv)
5545 return;
5546
5547 board = priv->board;
5548 kfree(priv);
5549 priv = pciserial_init_ports(dev, board);
5550
5551 if (!IS_ERR(priv)) {
5552 pci_set_drvdata(dev, priv);
5553 }
5554 }
5555
5556 static const struct pci_error_handlers serial8250_err_handler = {
5557 .error_detected = serial8250_io_error_detected,
5558 .slot_reset = serial8250_io_slot_reset,
5559 .resume = serial8250_io_resume,
5560 };
5561
5562 static struct pci_driver serial_pci_driver = {
5563 .name = "serial",
5564 .probe = pciserial_init_one,
5565 .remove = pciserial_remove_one,
5566 #ifdef CONFIG_PM
5567 .suspend = pciserial_suspend_one,
5568 .resume = pciserial_resume_one,
5569 #endif
5570 .id_table = serial_pci_tbl,
5571 .err_handler = &serial8250_err_handler,
5572 };
5573
5574 module_pci_driver(serial_pci_driver);
5575
5576 MODULE_LICENSE("GPL");
5577 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5578 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
5579