1 /*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33, aic3007.
16 *
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 and aic3007 is as follows:
19 * aic32/aic3007 | aic31
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
33 */
34
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/pm.h>
40 #include <linux/i2c.h>
41 #include <linux/gpio.h>
42 #include <linux/regulator/consumer.h>
43 #include <linux/of.h>
44 #include <linux/of_gpio.h>
45 #include <linux/slab.h>
46 #include <sound/core.h>
47 #include <sound/pcm.h>
48 #include <sound/pcm_params.h>
49 #include <sound/soc.h>
50 #include <sound/initval.h>
51 #include <sound/tlv.h>
52 #include <sound/tlv320aic3x.h>
53
54 #include "tlv320aic3x.h"
55
56 #define AIC3X_NUM_SUPPLIES 4
57 static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
58 "IOVDD", /* I/O Voltage */
59 "DVDD", /* Digital Core Voltage */
60 "AVDD", /* Analog DAC Voltage */
61 "DRVDD", /* ADC Analog and Output Driver Voltage */
62 };
63
64 static LIST_HEAD(reset_list);
65
66 struct aic3x_priv;
67
68 struct aic3x_disable_nb {
69 struct notifier_block nb;
70 struct aic3x_priv *aic3x;
71 };
72
73 /* codec private data */
74 struct aic3x_priv {
75 struct snd_soc_codec *codec;
76 struct regmap *regmap;
77 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
78 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
79 struct aic3x_setup_data *setup;
80 unsigned int sysclk;
81 struct list_head list;
82 int master;
83 int gpio_reset;
84 int power;
85 #define AIC3X_MODEL_3X 0
86 #define AIC3X_MODEL_33 1
87 #define AIC3X_MODEL_3007 2
88 u16 model;
89
90 /* Selects the micbias voltage */
91 enum aic3x_micbias_voltage micbias_vg;
92 };
93
94 static const struct reg_default aic3x_reg[] = {
95 { 0, 0x00 }, { 1, 0x00 }, { 2, 0x00 }, { 3, 0x10 },
96 { 4, 0x04 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 },
97 { 8, 0x00 }, { 9, 0x00 }, { 10, 0x00 }, { 11, 0x01 },
98 { 12, 0x00 }, { 13, 0x00 }, { 14, 0x00 }, { 15, 0x80 },
99 { 16, 0x80 }, { 17, 0xff }, { 18, 0xff }, { 19, 0x78 },
100 { 20, 0x78 }, { 21, 0x78 }, { 22, 0x78 }, { 23, 0x78 },
101 { 24, 0x78 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0xfe },
102 { 28, 0x00 }, { 29, 0x00 }, { 30, 0xfe }, { 31, 0x00 },
103 { 32, 0x18 }, { 33, 0x18 }, { 34, 0x00 }, { 35, 0x00 },
104 { 36, 0x00 }, { 37, 0x00 }, { 38, 0x00 }, { 39, 0x00 },
105 { 40, 0x00 }, { 41, 0x00 }, { 42, 0x00 }, { 43, 0x80 },
106 { 44, 0x80 }, { 45, 0x00 }, { 46, 0x00 }, { 47, 0x00 },
107 { 48, 0x00 }, { 49, 0x00 }, { 50, 0x00 }, { 51, 0x04 },
108 { 52, 0x00 }, { 53, 0x00 }, { 54, 0x00 }, { 55, 0x00 },
109 { 56, 0x00 }, { 57, 0x00 }, { 58, 0x04 }, { 59, 0x00 },
110 { 60, 0x00 }, { 61, 0x00 }, { 62, 0x00 }, { 63, 0x00 },
111 { 64, 0x00 }, { 65, 0x04 }, { 66, 0x00 }, { 67, 0x00 },
112 { 68, 0x00 }, { 69, 0x00 }, { 70, 0x00 }, { 71, 0x00 },
113 { 72, 0x04 }, { 73, 0x00 }, { 74, 0x00 }, { 75, 0x00 },
114 { 76, 0x00 }, { 77, 0x00 }, { 78, 0x00 }, { 79, 0x00 },
115 { 80, 0x00 }, { 81, 0x00 }, { 82, 0x00 }, { 83, 0x00 },
116 { 84, 0x00 }, { 85, 0x00 }, { 86, 0x00 }, { 87, 0x00 },
117 { 88, 0x00 }, { 89, 0x00 }, { 90, 0x00 }, { 91, 0x00 },
118 { 92, 0x00 }, { 93, 0x00 }, { 94, 0x00 }, { 95, 0x00 },
119 { 96, 0x00 }, { 97, 0x00 }, { 98, 0x00 }, { 99, 0x00 },
120 { 100, 0x00 }, { 101, 0x00 }, { 102, 0x02 }, { 103, 0x00 },
121 { 104, 0x00 }, { 105, 0x00 }, { 106, 0x00 }, { 107, 0x00 },
122 { 108, 0x00 }, { 109, 0x00 },
123 };
124
aic3x_volatile_reg(struct device * dev,unsigned int reg)125 static bool aic3x_volatile_reg(struct device *dev, unsigned int reg)
126 {
127 switch (reg) {
128 case AIC3X_RESET:
129 return true;
130 default:
131 return false;
132 }
133 }
134
135 static const struct regmap_config aic3x_regmap = {
136 .reg_bits = 8,
137 .val_bits = 8,
138
139 .max_register = DAC_ICC_ADJ,
140 .reg_defaults = aic3x_reg,
141 .num_reg_defaults = ARRAY_SIZE(aic3x_reg),
142
143 .volatile_reg = aic3x_volatile_reg,
144
145 .cache_type = REGCACHE_RBTREE,
146 };
147
148 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
149 SOC_SINGLE_EXT(xname, reg, shift, mask, invert, \
150 snd_soc_dapm_get_volsw, snd_soc_dapm_put_volsw_aic3x)
151
152 /*
153 * All input lines are connected when !0xf and disconnected with 0xf bit field,
154 * so we have to use specific dapm_put call for input mixer
155 */
snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)156 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
157 struct snd_ctl_elem_value *ucontrol)
158 {
159 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
160 struct soc_mixer_control *mc =
161 (struct soc_mixer_control *)kcontrol->private_value;
162 unsigned int reg = mc->reg;
163 unsigned int shift = mc->shift;
164 int max = mc->max;
165 unsigned int mask = (1 << fls(max)) - 1;
166 unsigned int invert = mc->invert;
167 unsigned short val;
168 struct snd_soc_dapm_update update;
169 int connect, change;
170
171 val = (ucontrol->value.integer.value[0] & mask);
172
173 mask = 0xf;
174 if (val)
175 val = mask;
176
177 connect = !!val;
178
179 if (invert)
180 val = mask - val;
181
182 mask <<= shift;
183 val <<= shift;
184
185 change = snd_soc_test_bits(codec, reg, mask, val);
186 if (change) {
187 update.kcontrol = kcontrol;
188 update.reg = reg;
189 update.mask = mask;
190 update.val = val;
191
192 snd_soc_dapm_mixer_update_power(&codec->dapm, kcontrol, connect,
193 &update);
194 }
195
196 return change;
197 }
198
199 /*
200 * mic bias power on/off share the same register bits with
201 * output voltage of mic bias. when power on mic bias, we
202 * need reclaim it to voltage value.
203 * 0x0 = Powered off
204 * 0x1 = MICBIAS output is powered to 2.0V,
205 * 0x2 = MICBIAS output is powered to 2.5V
206 * 0x3 = MICBIAS output is connected to AVDD
207 */
mic_bias_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)208 static int mic_bias_event(struct snd_soc_dapm_widget *w,
209 struct snd_kcontrol *kcontrol, int event)
210 {
211 struct snd_soc_codec *codec = w->codec;
212 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
213
214 switch (event) {
215 case SND_SOC_DAPM_POST_PMU:
216 /* change mic bias voltage to user defined */
217 snd_soc_update_bits(codec, MICBIAS_CTRL,
218 MICBIAS_LEVEL_MASK,
219 aic3x->micbias_vg << MICBIAS_LEVEL_SHIFT);
220 break;
221
222 case SND_SOC_DAPM_PRE_PMD:
223 snd_soc_update_bits(codec, MICBIAS_CTRL,
224 MICBIAS_LEVEL_MASK, 0);
225 break;
226 }
227 return 0;
228 }
229
230 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
231 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
232 static const char *aic3x_left_hpcom_mux[] =
233 { "differential of HPLOUT", "constant VCM", "single-ended" };
234 static const char *aic3x_right_hpcom_mux[] =
235 { "differential of HPROUT", "constant VCM", "single-ended",
236 "differential of HPLCOM", "external feedback" };
237 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
238 static const char *aic3x_adc_hpf[] =
239 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
240
241 #define LDAC_ENUM 0
242 #define RDAC_ENUM 1
243 #define LHPCOM_ENUM 2
244 #define RHPCOM_ENUM 3
245 #define LINE1L_2_L_ENUM 4
246 #define LINE1L_2_R_ENUM 5
247 #define LINE1R_2_L_ENUM 6
248 #define LINE1R_2_R_ENUM 7
249 #define LINE2L_ENUM 8
250 #define LINE2R_ENUM 9
251 #define ADC_HPF_ENUM 10
252
253 static const struct soc_enum aic3x_enum[] = {
254 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
255 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
256 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
257 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
258 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
259 SOC_ENUM_SINGLE(LINE1L_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
260 SOC_ENUM_SINGLE(LINE1R_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
261 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
262 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
263 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
264 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
265 };
266
267 static const char *aic3x_agc_level[] =
268 { "-5.5dB", "-8dB", "-10dB", "-12dB", "-14dB", "-17dB", "-20dB", "-24dB" };
269 static const struct soc_enum aic3x_agc_level_enum[] = {
270 SOC_ENUM_SINGLE(LAGC_CTRL_A, 4, 8, aic3x_agc_level),
271 SOC_ENUM_SINGLE(RAGC_CTRL_A, 4, 8, aic3x_agc_level),
272 };
273
274 static const char *aic3x_agc_attack[] = { "8ms", "11ms", "16ms", "20ms" };
275 static const struct soc_enum aic3x_agc_attack_enum[] = {
276 SOC_ENUM_SINGLE(LAGC_CTRL_A, 2, 4, aic3x_agc_attack),
277 SOC_ENUM_SINGLE(RAGC_CTRL_A, 2, 4, aic3x_agc_attack),
278 };
279
280 static const char *aic3x_agc_decay[] = { "100ms", "200ms", "400ms", "500ms" };
281 static const struct soc_enum aic3x_agc_decay_enum[] = {
282 SOC_ENUM_SINGLE(LAGC_CTRL_A, 0, 4, aic3x_agc_decay),
283 SOC_ENUM_SINGLE(RAGC_CTRL_A, 0, 4, aic3x_agc_decay),
284 };
285
286 /*
287 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
288 */
289 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
290 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
291 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
292 /*
293 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
294 * Step size is approximately 0.5 dB over most of the scale but increasing
295 * near the very low levels.
296 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
297 * but having increasing dB difference below that (and where it doesn't count
298 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
299 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
300 */
301 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
302
303 static const struct snd_kcontrol_new aic3x_snd_controls[] = {
304 /* Output */
305 SOC_DOUBLE_R_TLV("PCM Playback Volume",
306 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
307
308 /*
309 * Output controls that map to output mixer switches. Note these are
310 * only for swapped L-to-R and R-to-L routes. See below stereo controls
311 * for direct L-to-L and R-to-R routes.
312 */
313 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
314 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
315 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
316 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
317 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
318 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
319
320 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
321 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
322 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
323 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
324 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
325 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
326
327 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
328 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
329 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
330 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
331 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
332 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
333
334 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
335 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
336 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
337 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
338 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
339 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
340
341 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
342 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
343 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
344 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
345 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
346 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
347
348 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
349 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
350 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
351 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
352 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
353 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
354
355 /* Stereo output controls for direct L-to-L and R-to-R routes */
356 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
357 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
358 0, 118, 1, output_stage_tlv),
359 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
360 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
361 0, 118, 1, output_stage_tlv),
362 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
363 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
364 0, 118, 1, output_stage_tlv),
365
366 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
367 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
368 0, 118, 1, output_stage_tlv),
369 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
370 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
371 0, 118, 1, output_stage_tlv),
372 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
373 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
374 0, 118, 1, output_stage_tlv),
375
376 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
377 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
378 0, 118, 1, output_stage_tlv),
379 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
380 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
381 0, 118, 1, output_stage_tlv),
382 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
383 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
384 0, 118, 1, output_stage_tlv),
385
386 /* Output pin mute controls */
387 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
388 0x01, 0),
389 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
390 0x01, 0),
391 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
392 0x01, 0),
393
394 /*
395 * Note: enable Automatic input Gain Controller with care. It can
396 * adjust PGA to max value when ADC is on and will never go back.
397 */
398 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
399 SOC_ENUM("Left AGC Target level", aic3x_agc_level_enum[0]),
400 SOC_ENUM("Right AGC Target level", aic3x_agc_level_enum[1]),
401 SOC_ENUM("Left AGC Attack time", aic3x_agc_attack_enum[0]),
402 SOC_ENUM("Right AGC Attack time", aic3x_agc_attack_enum[1]),
403 SOC_ENUM("Left AGC Decay time", aic3x_agc_decay_enum[0]),
404 SOC_ENUM("Right AGC Decay time", aic3x_agc_decay_enum[1]),
405
406 /* De-emphasis */
407 SOC_DOUBLE("De-emphasis Switch", AIC3X_CODEC_DFILT_CTRL, 2, 0, 0x01, 0),
408
409 /* Input */
410 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
411 0, 119, 0, adc_tlv),
412 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
413
414 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
415 };
416
417 static const struct snd_kcontrol_new aic3x_mono_controls[] = {
418 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
419 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
420 0, 118, 1, output_stage_tlv),
421 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
422 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
423 0, 118, 1, output_stage_tlv),
424 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
425 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
426 0, 118, 1, output_stage_tlv),
427
428 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
429 };
430
431 /*
432 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
433 */
434 static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
435
436 static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
437 SOC_DOUBLE_TLV("Class-D Playback Volume", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
438
439 /* Left DAC Mux */
440 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
441 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
442
443 /* Right DAC Mux */
444 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
445 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
446
447 /* Left HPCOM Mux */
448 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
449 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
450
451 /* Right HPCOM Mux */
452 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
453 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
454
455 /* Left Line Mixer */
456 static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
457 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
458 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
459 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
460 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
461 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
462 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
463 };
464
465 /* Right Line Mixer */
466 static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
467 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
468 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
469 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
470 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
471 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
472 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
473 };
474
475 /* Mono Mixer */
476 static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
477 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
478 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
479 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
480 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
481 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
482 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
483 };
484
485 /* Left HP Mixer */
486 static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
487 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
488 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
489 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
490 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
491 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
492 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
493 };
494
495 /* Right HP Mixer */
496 static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
497 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
498 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
499 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
500 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
501 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
502 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
503 };
504
505 /* Left HPCOM Mixer */
506 static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
507 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
508 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
509 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
510 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
511 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
512 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
513 };
514
515 /* Right HPCOM Mixer */
516 static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
517 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
518 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
519 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
520 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
521 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
522 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
523 };
524
525 /* Left PGA Mixer */
526 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
527 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
528 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
529 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
530 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
531 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
532 };
533
534 /* Right PGA Mixer */
535 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
536 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
537 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
538 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
539 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
540 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
541 };
542
543 /* Left Line1 Mux */
544 static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls =
545 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_L_ENUM]);
546 static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls =
547 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_R_ENUM]);
548
549 /* Right Line1 Mux */
550 static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls =
551 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_R_ENUM]);
552 static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls =
553 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_L_ENUM]);
554
555 /* Left Line2 Mux */
556 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
557 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
558
559 /* Right Line2 Mux */
560 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
561 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
562
563 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
564 /* Left DAC to Left Outputs */
565 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
566 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
567 &aic3x_left_dac_mux_controls),
568 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
569 &aic3x_left_hpcom_mux_controls),
570 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
571 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
572 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
573
574 /* Right DAC to Right Outputs */
575 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
576 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
577 &aic3x_right_dac_mux_controls),
578 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
579 &aic3x_right_hpcom_mux_controls),
580 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
581 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
582 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
583
584 /* Inputs to Left ADC */
585 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
586 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
587 &aic3x_left_pga_mixer_controls[0],
588 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
589 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
590 &aic3x_left_line1l_mux_controls),
591 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
592 &aic3x_left_line1r_mux_controls),
593 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
594 &aic3x_left_line2_mux_controls),
595
596 /* Inputs to Right ADC */
597 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
598 LINE1R_2_RADC_CTRL, 2, 0),
599 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
600 &aic3x_right_pga_mixer_controls[0],
601 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
602 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
603 &aic3x_right_line1l_mux_controls),
604 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
605 &aic3x_right_line1r_mux_controls),
606 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
607 &aic3x_right_line2_mux_controls),
608
609 /*
610 * Not a real mic bias widget but similar function. This is for dynamic
611 * control of GPIO1 digital mic modulator clock output function when
612 * using digital mic.
613 */
614 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
615 AIC3X_GPIO1_REG, 4, 0xf,
616 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
617 AIC3X_GPIO1_FUNC_DISABLED),
618
619 /*
620 * Also similar function like mic bias. Selects digital mic with
621 * configurable oversampling rate instead of ADC converter.
622 */
623 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
624 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
625 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
626 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
627 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
628 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
629
630 /* Mic Bias */
631 SND_SOC_DAPM_SUPPLY("Mic Bias", MICBIAS_CTRL, 6, 0,
632 mic_bias_event,
633 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
634
635 /* Output mixers */
636 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
637 &aic3x_left_line_mixer_controls[0],
638 ARRAY_SIZE(aic3x_left_line_mixer_controls)),
639 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
640 &aic3x_right_line_mixer_controls[0],
641 ARRAY_SIZE(aic3x_right_line_mixer_controls)),
642 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
643 &aic3x_left_hp_mixer_controls[0],
644 ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
645 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
646 &aic3x_right_hp_mixer_controls[0],
647 ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
648 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
649 &aic3x_left_hpcom_mixer_controls[0],
650 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
651 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
652 &aic3x_right_hpcom_mixer_controls[0],
653 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
654
655 SND_SOC_DAPM_OUTPUT("LLOUT"),
656 SND_SOC_DAPM_OUTPUT("RLOUT"),
657 SND_SOC_DAPM_OUTPUT("HPLOUT"),
658 SND_SOC_DAPM_OUTPUT("HPROUT"),
659 SND_SOC_DAPM_OUTPUT("HPLCOM"),
660 SND_SOC_DAPM_OUTPUT("HPRCOM"),
661
662 SND_SOC_DAPM_INPUT("MIC3L"),
663 SND_SOC_DAPM_INPUT("MIC3R"),
664 SND_SOC_DAPM_INPUT("LINE1L"),
665 SND_SOC_DAPM_INPUT("LINE1R"),
666 SND_SOC_DAPM_INPUT("LINE2L"),
667 SND_SOC_DAPM_INPUT("LINE2R"),
668
669 /*
670 * Virtual output pin to detection block inside codec. This can be
671 * used to keep codec bias on if gpio or detection features are needed.
672 * Force pin on or construct a path with an input jack and mic bias
673 * widgets.
674 */
675 SND_SOC_DAPM_OUTPUT("Detection"),
676 };
677
678 static const struct snd_soc_dapm_widget aic3x_dapm_mono_widgets[] = {
679 /* Mono Output */
680 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
681
682 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
683 &aic3x_mono_mixer_controls[0],
684 ARRAY_SIZE(aic3x_mono_mixer_controls)),
685
686 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
687 };
688
689 static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
690 /* Class-D outputs */
691 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
692 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
693
694 SND_SOC_DAPM_OUTPUT("SPOP"),
695 SND_SOC_DAPM_OUTPUT("SPOM"),
696 };
697
698 static const struct snd_soc_dapm_route intercon[] = {
699 /* Left Input */
700 {"Left Line1L Mux", "single-ended", "LINE1L"},
701 {"Left Line1L Mux", "differential", "LINE1L"},
702 {"Left Line1R Mux", "single-ended", "LINE1R"},
703 {"Left Line1R Mux", "differential", "LINE1R"},
704
705 {"Left Line2L Mux", "single-ended", "LINE2L"},
706 {"Left Line2L Mux", "differential", "LINE2L"},
707
708 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
709 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
710 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
711 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
712 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
713
714 {"Left ADC", NULL, "Left PGA Mixer"},
715 {"Left ADC", NULL, "GPIO1 dmic modclk"},
716
717 /* Right Input */
718 {"Right Line1R Mux", "single-ended", "LINE1R"},
719 {"Right Line1R Mux", "differential", "LINE1R"},
720 {"Right Line1L Mux", "single-ended", "LINE1L"},
721 {"Right Line1L Mux", "differential", "LINE1L"},
722
723 {"Right Line2R Mux", "single-ended", "LINE2R"},
724 {"Right Line2R Mux", "differential", "LINE2R"},
725
726 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
727 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
728 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
729 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
730 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
731
732 {"Right ADC", NULL, "Right PGA Mixer"},
733 {"Right ADC", NULL, "GPIO1 dmic modclk"},
734
735 /*
736 * Logical path between digital mic enable and GPIO1 modulator clock
737 * output function
738 */
739 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
740 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
741 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
742
743 /* Left DAC Output */
744 {"Left DAC Mux", "DAC_L1", "Left DAC"},
745 {"Left DAC Mux", "DAC_L2", "Left DAC"},
746 {"Left DAC Mux", "DAC_L3", "Left DAC"},
747
748 /* Right DAC Output */
749 {"Right DAC Mux", "DAC_R1", "Right DAC"},
750 {"Right DAC Mux", "DAC_R2", "Right DAC"},
751 {"Right DAC Mux", "DAC_R3", "Right DAC"},
752
753 /* Left Line Output */
754 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
755 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
756 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
757 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
758 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
759 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
760
761 {"Left Line Out", NULL, "Left Line Mixer"},
762 {"Left Line Out", NULL, "Left DAC Mux"},
763 {"LLOUT", NULL, "Left Line Out"},
764
765 /* Right Line Output */
766 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
767 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
768 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
769 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
770 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
771 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
772
773 {"Right Line Out", NULL, "Right Line Mixer"},
774 {"Right Line Out", NULL, "Right DAC Mux"},
775 {"RLOUT", NULL, "Right Line Out"},
776
777 /* Left HP Output */
778 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
779 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
780 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
781 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
782 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
783 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
784
785 {"Left HP Out", NULL, "Left HP Mixer"},
786 {"Left HP Out", NULL, "Left DAC Mux"},
787 {"HPLOUT", NULL, "Left HP Out"},
788
789 /* Right HP Output */
790 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
791 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
792 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
793 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
794 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
795 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
796
797 {"Right HP Out", NULL, "Right HP Mixer"},
798 {"Right HP Out", NULL, "Right DAC Mux"},
799 {"HPROUT", NULL, "Right HP Out"},
800
801 /* Left HPCOM Output */
802 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
803 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
804 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
805 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
806 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
807 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
808
809 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
810 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
811 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
812 {"Left HP Com", NULL, "Left HPCOM Mux"},
813 {"HPLCOM", NULL, "Left HP Com"},
814
815 /* Right HPCOM Output */
816 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
817 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
818 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
819 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
820 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
821 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
822
823 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
824 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
825 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
826 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
827 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
828 {"Right HP Com", NULL, "Right HPCOM Mux"},
829 {"HPRCOM", NULL, "Right HP Com"},
830 };
831
832 static const struct snd_soc_dapm_route intercon_mono[] = {
833 /* Mono Output */
834 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
835 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
836 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
837 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
838 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
839 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
840 {"Mono Out", NULL, "Mono Mixer"},
841 {"MONO_LOUT", NULL, "Mono Out"},
842 };
843
844 static const struct snd_soc_dapm_route intercon_3007[] = {
845 /* Class-D outputs */
846 {"Left Class-D Out", NULL, "Left Line Out"},
847 {"Right Class-D Out", NULL, "Left Line Out"},
848 {"SPOP", NULL, "Left Class-D Out"},
849 {"SPOM", NULL, "Right Class-D Out"},
850 };
851
aic3x_add_widgets(struct snd_soc_codec * codec)852 static int aic3x_add_widgets(struct snd_soc_codec *codec)
853 {
854 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
855 struct snd_soc_dapm_context *dapm = &codec->dapm;
856
857 switch (aic3x->model) {
858 case AIC3X_MODEL_3X:
859 case AIC3X_MODEL_33:
860 snd_soc_dapm_new_controls(dapm, aic3x_dapm_mono_widgets,
861 ARRAY_SIZE(aic3x_dapm_mono_widgets));
862 snd_soc_dapm_add_routes(dapm, intercon_mono,
863 ARRAY_SIZE(intercon_mono));
864 break;
865 case AIC3X_MODEL_3007:
866 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
867 ARRAY_SIZE(aic3007_dapm_widgets));
868 snd_soc_dapm_add_routes(dapm, intercon_3007,
869 ARRAY_SIZE(intercon_3007));
870 break;
871 }
872
873 return 0;
874 }
875
aic3x_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)876 static int aic3x_hw_params(struct snd_pcm_substream *substream,
877 struct snd_pcm_hw_params *params,
878 struct snd_soc_dai *dai)
879 {
880 struct snd_soc_codec *codec = dai->codec;
881 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
882 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
883 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
884 u16 d, pll_d = 1;
885 int clk;
886
887 /* select data word length */
888 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
889 switch (params_width(params)) {
890 case 16:
891 break;
892 case 20:
893 data |= (0x01 << 4);
894 break;
895 case 24:
896 data |= (0x02 << 4);
897 break;
898 case 32:
899 data |= (0x03 << 4);
900 break;
901 }
902 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data);
903
904 /* Fsref can be 44100 or 48000 */
905 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
906
907 /* Try to find a value for Q which allows us to bypass the PLL and
908 * generate CODEC_CLK directly. */
909 for (pll_q = 2; pll_q < 18; pll_q++)
910 if (aic3x->sysclk / (128 * pll_q) == fsref) {
911 bypass_pll = 1;
912 break;
913 }
914
915 if (bypass_pll) {
916 pll_q &= 0xf;
917 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
918 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
919 /* disable PLL if it is bypassed */
920 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0);
921
922 } else {
923 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
924 /* enable PLL when it is used */
925 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
926 PLL_ENABLE, PLL_ENABLE);
927 }
928
929 /* Route Left DAC to left channel input and
930 * right DAC to right channel input */
931 data = (LDAC2LCH | RDAC2RCH);
932 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
933 if (params_rate(params) >= 64000)
934 data |= DUAL_RATE_MODE;
935 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
936
937 /* codec sample rate select */
938 data = (fsref * 20) / params_rate(params);
939 if (params_rate(params) < 64000)
940 data /= 2;
941 data /= 5;
942 data -= 2;
943 data |= (data << 4);
944 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
945
946 if (bypass_pll)
947 return 0;
948
949 /* Use PLL, compute appropriate setup for j, d, r and p, the closest
950 * one wins the game. Try with d==0 first, next with d!=0.
951 * Constraints for j are according to the datasheet.
952 * The sysclk is divided by 1000 to prevent integer overflows.
953 */
954
955 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
956
957 for (r = 1; r <= 16; r++)
958 for (p = 1; p <= 8; p++) {
959 for (j = 4; j <= 55; j++) {
960 /* This is actually 1000*((j+(d/10000))*r)/p
961 * The term had to be converted to get
962 * rid of the division by 10000; d = 0 here
963 */
964 int tmp_clk = (1000 * j * r) / p;
965
966 /* Check whether this values get closer than
967 * the best ones we had before
968 */
969 if (abs(codec_clk - tmp_clk) <
970 abs(codec_clk - last_clk)) {
971 pll_j = j; pll_d = 0;
972 pll_r = r; pll_p = p;
973 last_clk = tmp_clk;
974 }
975
976 /* Early exit for exact matches */
977 if (tmp_clk == codec_clk)
978 goto found;
979 }
980 }
981
982 /* try with d != 0 */
983 for (p = 1; p <= 8; p++) {
984 j = codec_clk * p / 1000;
985
986 if (j < 4 || j > 11)
987 continue;
988
989 /* do not use codec_clk here since we'd loose precision */
990 d = ((2048 * p * fsref) - j * aic3x->sysclk)
991 * 100 / (aic3x->sysclk/100);
992
993 clk = (10000 * j + d) / (10 * p);
994
995 /* check whether this values get closer than the best
996 * ones we had before */
997 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
998 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
999 last_clk = clk;
1000 }
1001
1002 /* Early exit for exact matches */
1003 if (clk == codec_clk)
1004 goto found;
1005 }
1006
1007 if (last_clk == 0) {
1008 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
1009 return -EINVAL;
1010 }
1011
1012 found:
1013 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLLP_MASK, pll_p);
1014 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG,
1015 pll_r << PLLR_SHIFT);
1016 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
1017 snd_soc_write(codec, AIC3X_PLL_PROGC_REG,
1018 (pll_d >> 6) << PLLD_MSB_SHIFT);
1019 snd_soc_write(codec, AIC3X_PLL_PROGD_REG,
1020 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
1021
1022 return 0;
1023 }
1024
aic3x_mute(struct snd_soc_dai * dai,int mute)1025 static int aic3x_mute(struct snd_soc_dai *dai, int mute)
1026 {
1027 struct snd_soc_codec *codec = dai->codec;
1028 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON;
1029 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON;
1030
1031 if (mute) {
1032 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
1033 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
1034 } else {
1035 snd_soc_write(codec, LDAC_VOL, ldac_reg);
1036 snd_soc_write(codec, RDAC_VOL, rdac_reg);
1037 }
1038
1039 return 0;
1040 }
1041
aic3x_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)1042 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1043 int clk_id, unsigned int freq, int dir)
1044 {
1045 struct snd_soc_codec *codec = codec_dai->codec;
1046 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1047
1048 /* set clock on MCLK or GPIO2 or BCLK */
1049 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK,
1050 clk_id << PLLCLK_IN_SHIFT);
1051 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK,
1052 clk_id << CLKDIV_IN_SHIFT);
1053
1054 aic3x->sysclk = freq;
1055 return 0;
1056 }
1057
aic3x_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)1058 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
1059 unsigned int fmt)
1060 {
1061 struct snd_soc_codec *codec = codec_dai->codec;
1062 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1063 u8 iface_areg, iface_breg;
1064 int delay = 0;
1065
1066 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
1067 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
1068
1069 /* set master/slave audio interface */
1070 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1071 case SND_SOC_DAIFMT_CBM_CFM:
1072 aic3x->master = 1;
1073 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1074 break;
1075 case SND_SOC_DAIFMT_CBS_CFS:
1076 aic3x->master = 0;
1077 iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER);
1078 break;
1079 default:
1080 return -EINVAL;
1081 }
1082
1083 /*
1084 * match both interface format and signal polarities since they
1085 * are fixed
1086 */
1087 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1088 SND_SOC_DAIFMT_INV_MASK)) {
1089 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
1090 break;
1091 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1092 delay = 1;
1093 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
1094 iface_breg |= (0x01 << 6);
1095 break;
1096 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
1097 iface_breg |= (0x02 << 6);
1098 break;
1099 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
1100 iface_breg |= (0x03 << 6);
1101 break;
1102 default:
1103 return -EINVAL;
1104 }
1105
1106 /* set iface */
1107 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1108 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1109 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
1110
1111 return 0;
1112 }
1113
aic3x_regulator_event(struct notifier_block * nb,unsigned long event,void * data)1114 static int aic3x_regulator_event(struct notifier_block *nb,
1115 unsigned long event, void *data)
1116 {
1117 struct aic3x_disable_nb *disable_nb =
1118 container_of(nb, struct aic3x_disable_nb, nb);
1119 struct aic3x_priv *aic3x = disable_nb->aic3x;
1120
1121 if (event & REGULATOR_EVENT_DISABLE) {
1122 /*
1123 * Put codec to reset and require cache sync as at least one
1124 * of the supplies was disabled
1125 */
1126 if (gpio_is_valid(aic3x->gpio_reset))
1127 gpio_set_value(aic3x->gpio_reset, 0);
1128 regcache_mark_dirty(aic3x->regmap);
1129 }
1130
1131 return 0;
1132 }
1133
aic3x_set_power(struct snd_soc_codec * codec,int power)1134 static int aic3x_set_power(struct snd_soc_codec *codec, int power)
1135 {
1136 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1137 unsigned int pll_c, pll_d;
1138 int ret;
1139
1140 if (power) {
1141 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1142 aic3x->supplies);
1143 if (ret)
1144 goto out;
1145 aic3x->power = 1;
1146
1147 if (gpio_is_valid(aic3x->gpio_reset)) {
1148 udelay(1);
1149 gpio_set_value(aic3x->gpio_reset, 1);
1150 }
1151
1152 /* Sync reg_cache with the hardware */
1153 regcache_cache_only(aic3x->regmap, false);
1154 regcache_sync(aic3x->regmap);
1155
1156 /* Rewrite paired PLL D registers in case cached sync skipped
1157 * writing one of them and thus caused other one also not
1158 * being written
1159 */
1160 pll_c = snd_soc_read(codec, AIC3X_PLL_PROGC_REG);
1161 pll_d = snd_soc_read(codec, AIC3X_PLL_PROGD_REG);
1162 if (pll_c == aic3x_reg[AIC3X_PLL_PROGC_REG].def ||
1163 pll_d == aic3x_reg[AIC3X_PLL_PROGD_REG].def) {
1164 snd_soc_write(codec, AIC3X_PLL_PROGC_REG, pll_c);
1165 snd_soc_write(codec, AIC3X_PLL_PROGD_REG, pll_d);
1166 }
1167 } else {
1168 /*
1169 * Do soft reset to this codec instance in order to clear
1170 * possible VDD leakage currents in case the supply regulators
1171 * remain on
1172 */
1173 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
1174 regcache_mark_dirty(aic3x->regmap);
1175 aic3x->power = 0;
1176 /* HW writes are needless when bias is off */
1177 regcache_cache_only(aic3x->regmap, true);
1178 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
1179 aic3x->supplies);
1180 }
1181 out:
1182 return ret;
1183 }
1184
aic3x_set_bias_level(struct snd_soc_codec * codec,enum snd_soc_bias_level level)1185 static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1186 enum snd_soc_bias_level level)
1187 {
1188 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1189
1190 switch (level) {
1191 case SND_SOC_BIAS_ON:
1192 break;
1193 case SND_SOC_BIAS_PREPARE:
1194 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY &&
1195 aic3x->master) {
1196 /* enable pll */
1197 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1198 PLL_ENABLE, PLL_ENABLE);
1199 }
1200 break;
1201 case SND_SOC_BIAS_STANDBY:
1202 if (!aic3x->power)
1203 aic3x_set_power(codec, 1);
1204 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE &&
1205 aic3x->master) {
1206 /* disable pll */
1207 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1208 PLL_ENABLE, 0);
1209 }
1210 break;
1211 case SND_SOC_BIAS_OFF:
1212 if (aic3x->power)
1213 aic3x_set_power(codec, 0);
1214 break;
1215 }
1216 codec->dapm.bias_level = level;
1217
1218 return 0;
1219 }
1220
1221 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1222 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1223 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE | \
1224 SNDRV_PCM_FMTBIT_S32_LE)
1225
1226 static const struct snd_soc_dai_ops aic3x_dai_ops = {
1227 .hw_params = aic3x_hw_params,
1228 .digital_mute = aic3x_mute,
1229 .set_sysclk = aic3x_set_dai_sysclk,
1230 .set_fmt = aic3x_set_dai_fmt,
1231 };
1232
1233 static struct snd_soc_dai_driver aic3x_dai = {
1234 .name = "tlv320aic3x-hifi",
1235 .playback = {
1236 .stream_name = "Playback",
1237 .channels_min = 2,
1238 .channels_max = 2,
1239 .rates = AIC3X_RATES,
1240 .formats = AIC3X_FORMATS,},
1241 .capture = {
1242 .stream_name = "Capture",
1243 .channels_min = 2,
1244 .channels_max = 2,
1245 .rates = AIC3X_RATES,
1246 .formats = AIC3X_FORMATS,},
1247 .ops = &aic3x_dai_ops,
1248 .symmetric_rates = 1,
1249 };
1250
aic3x_mono_init(struct snd_soc_codec * codec)1251 static void aic3x_mono_init(struct snd_soc_codec *codec)
1252 {
1253 /* DAC to Mono Line Out default volume and route to Output mixer */
1254 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1255 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1256
1257 /* unmute all outputs */
1258 snd_soc_update_bits(codec, MONOLOPM_CTRL, UNMUTE, UNMUTE);
1259
1260 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1261 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1262 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1263
1264 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1265 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1266 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1267 }
1268
1269 /*
1270 * initialise the AIC3X driver
1271 * register the mixer and dsp interfaces with the kernel
1272 */
aic3x_init(struct snd_soc_codec * codec)1273 static int aic3x_init(struct snd_soc_codec *codec)
1274 {
1275 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1276
1277 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1278 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
1279
1280 /* DAC default volume and mute */
1281 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1282 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1283
1284 /* DAC to HP default volume and route to Output mixer */
1285 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1286 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1287 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1288 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1289 /* DAC to Line Out default volume and route to Output mixer */
1290 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1291 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1292
1293 /* unmute all outputs */
1294 snd_soc_update_bits(codec, LLOPM_CTRL, UNMUTE, UNMUTE);
1295 snd_soc_update_bits(codec, RLOPM_CTRL, UNMUTE, UNMUTE);
1296 snd_soc_update_bits(codec, HPLOUT_CTRL, UNMUTE, UNMUTE);
1297 snd_soc_update_bits(codec, HPROUT_CTRL, UNMUTE, UNMUTE);
1298 snd_soc_update_bits(codec, HPLCOM_CTRL, UNMUTE, UNMUTE);
1299 snd_soc_update_bits(codec, HPRCOM_CTRL, UNMUTE, UNMUTE);
1300
1301 /* ADC default volume and unmute */
1302 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN);
1303 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN);
1304 /* By default route Line1 to ADC PGA mixer */
1305 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1306 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1307
1308 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1309 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1310 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1311 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1312 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1313 /* PGA to Line Out default volume, disconnect from Output Mixer */
1314 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1315 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1316
1317 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1318 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1319 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1320 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1321 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1322 /* Line2 Line Out default volume, disconnect from Output Mixer */
1323 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1324 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1325
1326 switch (aic3x->model) {
1327 case AIC3X_MODEL_3X:
1328 case AIC3X_MODEL_33:
1329 aic3x_mono_init(codec);
1330 break;
1331 case AIC3X_MODEL_3007:
1332 snd_soc_write(codec, CLASSD_CTRL, 0);
1333 break;
1334 }
1335
1336 return 0;
1337 }
1338
aic3x_is_shared_reset(struct aic3x_priv * aic3x)1339 static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x)
1340 {
1341 struct aic3x_priv *a;
1342
1343 list_for_each_entry(a, &reset_list, list) {
1344 if (gpio_is_valid(aic3x->gpio_reset) &&
1345 aic3x->gpio_reset == a->gpio_reset)
1346 return true;
1347 }
1348
1349 return false;
1350 }
1351
aic3x_probe(struct snd_soc_codec * codec)1352 static int aic3x_probe(struct snd_soc_codec *codec)
1353 {
1354 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1355 int ret, i;
1356
1357 INIT_LIST_HEAD(&aic3x->list);
1358 aic3x->codec = codec;
1359
1360 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
1361 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
1362 aic3x->disable_nb[i].aic3x = aic3x;
1363 ret = regulator_register_notifier(aic3x->supplies[i].consumer,
1364 &aic3x->disable_nb[i].nb);
1365 if (ret) {
1366 dev_err(codec->dev,
1367 "Failed to request regulator notifier: %d\n",
1368 ret);
1369 goto err_notif;
1370 }
1371 }
1372
1373 regcache_mark_dirty(aic3x->regmap);
1374 aic3x_init(codec);
1375
1376 if (aic3x->setup) {
1377 /* setup GPIO functions */
1378 snd_soc_write(codec, AIC3X_GPIO1_REG,
1379 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1380 snd_soc_write(codec, AIC3X_GPIO2_REG,
1381 (aic3x->setup->gpio_func[1] & 0xf) << 4);
1382 }
1383
1384 switch (aic3x->model) {
1385 case AIC3X_MODEL_3X:
1386 case AIC3X_MODEL_33:
1387 snd_soc_add_codec_controls(codec, aic3x_mono_controls,
1388 ARRAY_SIZE(aic3x_mono_controls));
1389 break;
1390 case AIC3X_MODEL_3007:
1391 snd_soc_add_codec_controls(codec,
1392 &aic3x_classd_amp_gain_ctrl, 1);
1393 break;
1394 }
1395
1396 /* set mic bias voltage */
1397 switch (aic3x->micbias_vg) {
1398 case AIC3X_MICBIAS_2_0V:
1399 case AIC3X_MICBIAS_2_5V:
1400 case AIC3X_MICBIAS_AVDDV:
1401 snd_soc_update_bits(codec, MICBIAS_CTRL,
1402 MICBIAS_LEVEL_MASK,
1403 (aic3x->micbias_vg) << MICBIAS_LEVEL_SHIFT);
1404 break;
1405 case AIC3X_MICBIAS_OFF:
1406 /*
1407 * noting to do. target won't enter here. This is just to avoid
1408 * compile time warning "warning: enumeration value
1409 * 'AIC3X_MICBIAS_OFF' not handled in switch"
1410 */
1411 break;
1412 }
1413
1414 aic3x_add_widgets(codec);
1415
1416 return 0;
1417
1418 err_notif:
1419 while (i--)
1420 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1421 &aic3x->disable_nb[i].nb);
1422 return ret;
1423 }
1424
aic3x_remove(struct snd_soc_codec * codec)1425 static int aic3x_remove(struct snd_soc_codec *codec)
1426 {
1427 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1428 int i;
1429
1430 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1431 list_del(&aic3x->list);
1432 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1433 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1434 &aic3x->disable_nb[i].nb);
1435
1436 return 0;
1437 }
1438
1439 static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
1440 .set_bias_level = aic3x_set_bias_level,
1441 .idle_bias_off = true,
1442 .probe = aic3x_probe,
1443 .remove = aic3x_remove,
1444 .controls = aic3x_snd_controls,
1445 .num_controls = ARRAY_SIZE(aic3x_snd_controls),
1446 .dapm_widgets = aic3x_dapm_widgets,
1447 .num_dapm_widgets = ARRAY_SIZE(aic3x_dapm_widgets),
1448 .dapm_routes = intercon,
1449 .num_dapm_routes = ARRAY_SIZE(intercon),
1450 };
1451
1452 /*
1453 * AIC3X 2 wire address can be up to 4 devices with device addresses
1454 * 0x18, 0x19, 0x1A, 0x1B
1455 */
1456
1457 static const struct i2c_device_id aic3x_i2c_id[] = {
1458 { "tlv320aic3x", AIC3X_MODEL_3X },
1459 { "tlv320aic33", AIC3X_MODEL_33 },
1460 { "tlv320aic3007", AIC3X_MODEL_3007 },
1461 { "tlv320aic3106", AIC3X_MODEL_3X },
1462 { }
1463 };
1464 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1465
1466 static const struct reg_default aic3007_class_d[] = {
1467 /* Class-D speaker driver init; datasheet p. 46 */
1468 { AIC3X_PAGE_SELECT, 0x0D },
1469 { 0xD, 0x0D },
1470 { 0x8, 0x5C },
1471 { 0x8, 0x5D },
1472 { 0x8, 0x5C },
1473 { AIC3X_PAGE_SELECT, 0x00 },
1474 };
1475
1476 /*
1477 * If the i2c layer weren't so broken, we could pass this kind of data
1478 * around
1479 */
aic3x_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)1480 static int aic3x_i2c_probe(struct i2c_client *i2c,
1481 const struct i2c_device_id *id)
1482 {
1483 struct aic3x_pdata *pdata = i2c->dev.platform_data;
1484 struct aic3x_priv *aic3x;
1485 struct aic3x_setup_data *ai3x_setup;
1486 struct device_node *np = i2c->dev.of_node;
1487 int ret, i;
1488 u32 value;
1489
1490 aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL);
1491 if (!aic3x)
1492 return -ENOMEM;
1493
1494 aic3x->regmap = devm_regmap_init_i2c(i2c, &aic3x_regmap);
1495 if (IS_ERR(aic3x->regmap)) {
1496 ret = PTR_ERR(aic3x->regmap);
1497 return ret;
1498 }
1499
1500 regcache_cache_only(aic3x->regmap, true);
1501
1502 i2c_set_clientdata(i2c, aic3x);
1503 if (pdata) {
1504 aic3x->gpio_reset = pdata->gpio_reset;
1505 aic3x->setup = pdata->setup;
1506 aic3x->micbias_vg = pdata->micbias_vg;
1507 } else if (np) {
1508 ai3x_setup = devm_kzalloc(&i2c->dev, sizeof(*ai3x_setup),
1509 GFP_KERNEL);
1510 if (!ai3x_setup)
1511 return -ENOMEM;
1512
1513 ret = of_get_named_gpio(np, "gpio-reset", 0);
1514 if (ret >= 0)
1515 aic3x->gpio_reset = ret;
1516 else
1517 aic3x->gpio_reset = -1;
1518
1519 if (of_property_read_u32_array(np, "ai3x-gpio-func",
1520 ai3x_setup->gpio_func, 2) >= 0) {
1521 aic3x->setup = ai3x_setup;
1522 }
1523
1524 if (!of_property_read_u32(np, "ai3x-micbias-vg", &value)) {
1525 switch (value) {
1526 case 1 :
1527 aic3x->micbias_vg = AIC3X_MICBIAS_2_0V;
1528 break;
1529 case 2 :
1530 aic3x->micbias_vg = AIC3X_MICBIAS_2_5V;
1531 break;
1532 case 3 :
1533 aic3x->micbias_vg = AIC3X_MICBIAS_AVDDV;
1534 break;
1535 default :
1536 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1537 dev_err(&i2c->dev, "Unsuitable MicBias voltage "
1538 "found in DT\n");
1539 }
1540 } else {
1541 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1542 }
1543
1544 } else {
1545 aic3x->gpio_reset = -1;
1546 }
1547
1548 aic3x->model = id->driver_data;
1549
1550 if (gpio_is_valid(aic3x->gpio_reset) &&
1551 !aic3x_is_shared_reset(aic3x)) {
1552 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
1553 if (ret != 0)
1554 goto err;
1555 gpio_direction_output(aic3x->gpio_reset, 0);
1556 }
1557
1558 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1559 aic3x->supplies[i].supply = aic3x_supply_names[i];
1560
1561 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(aic3x->supplies),
1562 aic3x->supplies);
1563 if (ret != 0) {
1564 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1565 goto err_gpio;
1566 }
1567
1568 if (aic3x->model == AIC3X_MODEL_3007) {
1569 ret = regmap_register_patch(aic3x->regmap, aic3007_class_d,
1570 ARRAY_SIZE(aic3007_class_d));
1571 if (ret != 0)
1572 dev_err(&i2c->dev, "Failed to init class D: %d\n",
1573 ret);
1574 }
1575
1576 ret = snd_soc_register_codec(&i2c->dev,
1577 &soc_codec_dev_aic3x, &aic3x_dai, 1);
1578
1579 if (ret != 0)
1580 goto err_gpio;
1581
1582 list_add(&aic3x->list, &reset_list);
1583
1584 return 0;
1585
1586 err_gpio:
1587 if (gpio_is_valid(aic3x->gpio_reset) &&
1588 !aic3x_is_shared_reset(aic3x))
1589 gpio_free(aic3x->gpio_reset);
1590 err:
1591 return ret;
1592 }
1593
aic3x_i2c_remove(struct i2c_client * client)1594 static int aic3x_i2c_remove(struct i2c_client *client)
1595 {
1596 struct aic3x_priv *aic3x = i2c_get_clientdata(client);
1597
1598 snd_soc_unregister_codec(&client->dev);
1599 if (gpio_is_valid(aic3x->gpio_reset) &&
1600 !aic3x_is_shared_reset(aic3x)) {
1601 gpio_set_value(aic3x->gpio_reset, 0);
1602 gpio_free(aic3x->gpio_reset);
1603 }
1604 return 0;
1605 }
1606
1607 #if defined(CONFIG_OF)
1608 static const struct of_device_id tlv320aic3x_of_match[] = {
1609 { .compatible = "ti,tlv320aic3x", },
1610 { .compatible = "ti,tlv320aic33" },
1611 { .compatible = "ti,tlv320aic3007" },
1612 { .compatible = "ti,tlv320aic3106" },
1613 {},
1614 };
1615 MODULE_DEVICE_TABLE(of, tlv320aic3x_of_match);
1616 #endif
1617
1618 /* machine i2c codec control layer */
1619 static struct i2c_driver aic3x_i2c_driver = {
1620 .driver = {
1621 .name = "tlv320aic3x-codec",
1622 .owner = THIS_MODULE,
1623 .of_match_table = of_match_ptr(tlv320aic3x_of_match),
1624 },
1625 .probe = aic3x_i2c_probe,
1626 .remove = aic3x_i2c_remove,
1627 .id_table = aic3x_i2c_id,
1628 };
1629
1630 module_i2c_driver(aic3x_i2c_driver);
1631
1632 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1633 MODULE_AUTHOR("Vladimir Barinov");
1634 MODULE_LICENSE("GPL");
1635