Lines Matching refs:vip
45 #define vip volatile int * macro
115 stat0 = *(vip)CIA_IOC_CIA_ERR; in conf_read()
116 *(vip)CIA_IOC_CIA_ERR = stat0; in conf_read()
118 *(vip)CIA_IOC_CIA_ERR; /* re-read to force write */ in conf_read()
122 cia_cfg = *(vip)CIA_IOC_CFG; in conf_read()
123 *(vip)CIA_IOC_CFG = (cia_cfg & ~3) | 1; in conf_read()
125 *(vip)CIA_IOC_CFG; in conf_read()
135 value = *(vip)addr; in conf_read()
148 *(vip)CIA_IOC_CFG = cia_cfg; in conf_read()
150 *(vip)CIA_IOC_CFG; in conf_read()
169 stat0 = *(vip)CIA_IOC_CIA_ERR; in conf_write()
170 *(vip)CIA_IOC_CIA_ERR = stat0; in conf_write()
172 *(vip)CIA_IOC_CIA_ERR; /* re-read to force write */ in conf_write()
176 cia_cfg = *(vip)CIA_IOC_CFG; in conf_write()
177 *(vip)CIA_IOC_CFG = (cia_cfg & ~3) | 1; in conf_write()
179 *(vip)CIA_IOC_CFG; in conf_write()
189 *(vip)addr = value; in conf_write()
191 *(vip)addr; /* read back to force the write */ in conf_write()
198 *(vip)CIA_IOC_CFG = cia_cfg; in conf_write()
200 *(vip)CIA_IOC_CFG; in conf_write()
259 *(vip)CIA_IOC_PCI_TBIA = 3; /* Flush all locked and unlocked. */ in cia_pci_tbi()
261 *(vip)CIA_IOC_PCI_TBIA; in cia_pci_tbi()
291 ctrl = *(vip)CIA_IOC_CIA_CTRL; in cia_pci_tbi_try2()
292 *(vip)CIA_IOC_CIA_CTRL = ctrl | CIA_CTRL_PCI_LOOP_EN; in cia_pci_tbi_try2()
294 *(vip)CIA_IOC_CIA_CTRL; in cia_pci_tbi_try2()
320 *(vip)CIA_IOC_CIA_CTRL = ctrl; in cia_pci_tbi_try2()
322 *(vip)CIA_IOC_CIA_CTRL; in cia_pci_tbi_try2()
339 *(vip)CIA_IOC_PCI_Wn_BASE(window) = CIA_BROKEN_TBIA_BASE | 3; in cia_prepare_tbia_workaround()
340 *(vip)CIA_IOC_PCI_Wn_MASK(window) in cia_prepare_tbia_workaround()
342 *(vip)CIA_IOC_PCI_Tn_BASE(window) = virt_to_phys(ppte) >> 2; in cia_prepare_tbia_workaround()
363 ctrl = *(vip)CIA_IOC_CIA_CTRL; in verify_tb_operation()
364 *(vip)CIA_IOC_CIA_CTRL = ctrl | CIA_CTRL_PCI_LOOP_EN; in verify_tb_operation()
366 *(vip)CIA_IOC_CIA_CTRL; in verify_tb_operation()
375 *(vip)CIA_IOC_TB_TAGn(0) = tag0; in verify_tb_operation()
376 *(vip)CIA_IOC_TB_TAGn(1) = 0; in verify_tb_operation()
377 *(vip)CIA_IOC_TB_TAGn(2) = 0; in verify_tb_operation()
378 *(vip)CIA_IOC_TB_TAGn(3) = 0; in verify_tb_operation()
379 *(vip)CIA_IOC_TB_TAGn(4) = 0; in verify_tb_operation()
380 *(vip)CIA_IOC_TB_TAGn(5) = 0; in verify_tb_operation()
381 *(vip)CIA_IOC_TB_TAGn(6) = 0; in verify_tb_operation()
382 *(vip)CIA_IOC_TB_TAGn(7) = 0; in verify_tb_operation()
383 *(vip)CIA_IOC_TBn_PAGEm(0,0) = pte0; in verify_tb_operation()
384 *(vip)CIA_IOC_TBn_PAGEm(0,1) = 0; in verify_tb_operation()
385 *(vip)CIA_IOC_TBn_PAGEm(0,2) = 0; in verify_tb_operation()
386 *(vip)CIA_IOC_TBn_PAGEm(0,3) = 0; in verify_tb_operation()
400 temp = *(vip)CIA_IOC_TB_TAGn(0); in verify_tb_operation()
406 temp = *(vip)CIA_IOC_TB_TAGn(1); in verify_tb_operation()
412 temp = *(vip)CIA_IOC_TBn_PAGEm(0,0); in verify_tb_operation()
446 temp = *(vip)CIA_IOC_TB_TAGn(0); in verify_tb_operation()
528 *(vip)CIA_IOC_TB_TAGn(0) = 2; in verify_tb_operation()
529 *(vip)CIA_IOC_TB_TAGn(1) = 2; in verify_tb_operation()
530 *(vip)CIA_IOC_TB_TAGn(2) = 2; in verify_tb_operation()
531 *(vip)CIA_IOC_TB_TAGn(3) = 2; in verify_tb_operation()
543 *(vip)CIA_IOC_CIA_CTRL = ctrl; in verify_tb_operation()
545 *(vip)CIA_IOC_CIA_CTRL; in verify_tb_operation()
551 *(vip)CIA_IOC_PCI_W0_BASE = 0; in verify_tb_operation()
552 *(vip)CIA_IOC_PCI_W1_BASE = 0; in verify_tb_operation()
581 saved_config.err_mask = *(vip)CIA_IOC_ERR_MASK; in cia_save_srm_settings()
582 saved_config.cia_ctrl = *(vip)CIA_IOC_CIA_CTRL; in cia_save_srm_settings()
583 saved_config.hae_mem = *(vip)CIA_IOC_HAE_MEM; in cia_save_srm_settings()
584 saved_config.hae_io = *(vip)CIA_IOC_HAE_IO; in cia_save_srm_settings()
585 saved_config.pci_dac_offset = *(vip)CIA_IOC_PCI_W_DAC; in cia_save_srm_settings()
588 saved_config.cia_cnfg = *(vip)CIA_IOC_CIA_CNFG; in cia_save_srm_settings()
594 saved_config.window[i].w_base = *(vip)CIA_IOC_PCI_Wn_BASE(i); in cia_save_srm_settings()
595 saved_config.window[i].w_mask = *(vip)CIA_IOC_PCI_Wn_MASK(i); in cia_save_srm_settings()
596 saved_config.window[i].t_base = *(vip)CIA_IOC_PCI_Tn_BASE(i); in cia_save_srm_settings()
607 *(vip)CIA_IOC_PCI_Wn_BASE(i) = saved_config.window[i].w_base; in cia_restore_srm_settings()
608 *(vip)CIA_IOC_PCI_Wn_MASK(i) = saved_config.window[i].w_mask; in cia_restore_srm_settings()
609 *(vip)CIA_IOC_PCI_Tn_BASE(i) = saved_config.window[i].t_base; in cia_restore_srm_settings()
612 *(vip)CIA_IOC_HAE_MEM = saved_config.hae_mem; in cia_restore_srm_settings()
613 *(vip)CIA_IOC_HAE_IO = saved_config.hae_io; in cia_restore_srm_settings()
614 *(vip)CIA_IOC_PCI_W_DAC = saved_config.pci_dac_offset; in cia_restore_srm_settings()
615 *(vip)CIA_IOC_ERR_MASK = saved_config.err_mask; in cia_restore_srm_settings()
616 *(vip)CIA_IOC_CIA_CTRL = saved_config.cia_ctrl; in cia_restore_srm_settings()
619 *(vip)CIA_IOC_CIA_CNFG = saved_config.cia_cnfg; in cia_restore_srm_settings()
635 cia_rev = *(vip)CIA_IOC_CIA_REV & CIA_REV_MASK; in do_init_arch()
643 temp = *(vip)CIA_IOC_ERR_MASK; in do_init_arch()
646 *(vip)CIA_IOC_ERR_MASK = temp; in do_init_arch()
649 temp = *(vip)CIA_IOC_CIA_ERR; in do_init_arch()
650 *(vip)CIA_IOC_CIA_ERR = temp; in do_init_arch()
653 temp = *(vip)CIA_IOC_CIA_CTRL; in do_init_arch()
655 *(vip)CIA_IOC_CIA_CTRL = temp; in do_init_arch()
660 *(vip)CIA_IOC_CFG = 0; in do_init_arch()
663 *(vip)CIA_IOC_HAE_MEM = 0; in do_init_arch()
664 *(vip)CIA_IOC_HAE_IO = 0; in do_init_arch()
670 temp = *(vip)CIA_IOC_CIA_CNFG; in do_init_arch()
672 *(vip)CIA_IOC_CIA_CNFG = temp; in do_init_arch()
677 *(vip)CIA_IOC_CIA_REV; in do_init_arch()
731 *(vip)CIA_IOC_PCI_W0_BASE = hose->sg_isa->dma_base | 3; in do_init_arch()
732 *(vip)CIA_IOC_PCI_W0_MASK = (hose->sg_isa->size - 1) & 0xfff00000; in do_init_arch()
733 *(vip)CIA_IOC_PCI_T0_BASE = virt_to_phys(hose->sg_isa->ptes) >> 2; in do_init_arch()
735 *(vip)CIA_IOC_PCI_W2_BASE = __direct_map_base | 1; in do_init_arch()
736 *(vip)CIA_IOC_PCI_W2_MASK = (__direct_map_size - 1) & 0xfff00000; in do_init_arch()
737 *(vip)CIA_IOC_PCI_T2_BASE = 0 >> 2; in do_init_arch()
755 *(vip)CIA_IOC_PCI_W3_BASE = 0; in do_init_arch()
757 *(vip)CIA_IOC_PCI_W1_BASE = 0; in do_init_arch()
760 *(vip)CIA_IOC_PCI_W3_BASE = 0; in do_init_arch()
762 *(vip)CIA_IOC_PCI_W3_BASE = 0x00000000 | 1 | 8; in do_init_arch()
763 *(vip)CIA_IOC_PCI_W3_MASK = 0xfff00000; in do_init_arch()
764 *(vip)CIA_IOC_PCI_T3_BASE = 0 >> 2; in do_init_arch()
767 *(vip)CIA_IOC_PCI_W_DAC = alpha_mv.pci_dac_offset >> 32; in do_init_arch()
825 jd = *(vip)CIA_IOC_CIA_ERR; in cia_pci_clr_err()
826 *(vip)CIA_IOC_CIA_ERR = jd; in cia_pci_clr_err()
828 *(vip)CIA_IOC_CIA_ERR; /* re-read to force write. */ in cia_pci_clr_err()
868 tmp = *(vip)CIA_IOC_PCI_W_DAC & 0xFFUL; in cia_decode_pci_error()