Lines Matching refs:base
29 static inline u16 sd_ctrl_read16(void __iomem *base, int addr) in sd_ctrl_read16() argument
31 return __raw_readw(base + addr); in sd_ctrl_read16()
34 static inline u32 sd_ctrl_read32(void __iomem *base, int addr) in sd_ctrl_read32() argument
36 return __raw_readw(base + addr) | in sd_ctrl_read32()
37 __raw_readw(base + addr + 2) << 16; in sd_ctrl_read32()
40 static inline void sd_ctrl_write16(void __iomem *base, int addr, u16 val) in sd_ctrl_write16() argument
42 __raw_writew(val, base + addr); in sd_ctrl_write16()
45 static inline void sd_ctrl_write32(void __iomem *base, int addr, u32 val) in sd_ctrl_write32() argument
47 __raw_writew(val, base + addr); in sd_ctrl_write32()
48 __raw_writew(val >> 16, base + addr + 2); in sd_ctrl_write32()
57 static int sdhi_intr(void __iomem *base) in sdhi_intr() argument
59 unsigned long state = sd_ctrl_read32(base, CTL_STATUS); in sdhi_intr()
62 sd_ctrl_write32(base, CTL_STATUS, ~ALL_ERROR); in sdhi_intr()
63 sd_ctrl_write32(base, CTL_IRQ_MASK, in sdhi_intr()
65 sd_ctrl_read32(base, CTL_IRQ_MASK)); in sdhi_intr()
69 sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_CMDRESPEND); in sdhi_intr()
70 sd_ctrl_write32(base, CTL_IRQ_MASK, in sdhi_intr()
72 sd_ctrl_read32(base, CTL_IRQ_MASK)); in sdhi_intr()
76 sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_RXRDY); in sdhi_intr()
77 sd_ctrl_write32(base, CTL_IRQ_MASK, in sdhi_intr()
79 sd_ctrl_read32(base, CTL_IRQ_MASK)); in sdhi_intr()
83 sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_DATAEND); in sdhi_intr()
84 sd_ctrl_write32(base, CTL_IRQ_MASK, in sdhi_intr()
86 sd_ctrl_read32(base, CTL_IRQ_MASK)); in sdhi_intr()
93 static int sdhi_boot_wait_resp_end(void __iomem *base) in sdhi_boot_wait_resp_end() argument
98 err = sdhi_intr(base); in sdhi_boot_wait_resp_end()
111 static void sdhi_boot_mmc_clk_stop(void __iomem *base) in sdhi_boot_mmc_clk_stop() argument
113 sd_ctrl_write16(base, CTL_CLK_AND_WAIT_CTL, 0x0000); in sdhi_boot_mmc_clk_stop()
115 sd_ctrl_write16(base, CTL_SD_CARD_CLK_CTL, ~CLK_MMC_ENABLE & in sdhi_boot_mmc_clk_stop()
116 sd_ctrl_read16(base, CTL_SD_CARD_CLK_CTL)); in sdhi_boot_mmc_clk_stop()
120 static void sdhi_boot_mmc_clk_start(void __iomem *base) in sdhi_boot_mmc_clk_start() argument
122 sd_ctrl_write16(base, CTL_SD_CARD_CLK_CTL, CLK_MMC_ENABLE | in sdhi_boot_mmc_clk_start()
123 sd_ctrl_read16(base, CTL_SD_CARD_CLK_CTL)); in sdhi_boot_mmc_clk_start()
125 sd_ctrl_write16(base, CTL_CLK_AND_WAIT_CTL, CLK_MMC_ENABLE); in sdhi_boot_mmc_clk_start()
129 static void sdhi_boot_reset(void __iomem *base) in sdhi_boot_reset() argument
131 sd_ctrl_write16(base, CTL_RESET_SD, 0x0000); in sdhi_boot_reset()
133 sd_ctrl_write16(base, CTL_RESET_SD, 0x0001); in sdhi_boot_reset()
143 static int sdhi_boot_mmc_set_ios(void __iomem *base, struct mmc_ios *ios) in sdhi_boot_mmc_set_ios() argument
145 if (sd_ctrl_read32(base, CTL_STATUS) & TMIO_STAT_CMD_BUSY) in sdhi_boot_mmc_set_ios()
149 sd_ctrl_write16(base, CTL_SD_CARD_CLK_CTL, in sdhi_boot_mmc_set_ios()
155 sdhi_boot_mmc_clk_stop(base); in sdhi_boot_mmc_set_ios()
160 sdhi_boot_mmc_clk_start(base); in sdhi_boot_mmc_set_ios()
166 sd_ctrl_write16(base, CTL_SD_MEM_CARD_OPT, 0x80e0); in sdhi_boot_mmc_set_ios()
169 sd_ctrl_write16(base, CTL_SD_MEM_CARD_OPT, 0x00e0); in sdhi_boot_mmc_set_ios()
189 static int sdhi_boot_request(void __iomem *base, struct mmc_command *cmd) in sdhi_boot_request() argument
204 sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_CMDRESPEND); in sdhi_boot_request()
206 sd_ctrl_write32(base, CTL_IRQ_MASK, TMIO_STAT_CMDRESPEND | in sdhi_boot_request()
207 sd_ctrl_read32(base, CTL_IRQ_MASK)); in sdhi_boot_request()
208 sd_ctrl_write32(base, CTL_ARG_REG, cmd->arg); in sdhi_boot_request()
209 sd_ctrl_write16(base, CTL_SD_CMD, c); in sdhi_boot_request()
212 sd_ctrl_write32(base, CTL_IRQ_MASK, in sdhi_boot_request()
214 sd_ctrl_read32(base, CTL_IRQ_MASK)); in sdhi_boot_request()
216 err = sdhi_boot_wait_resp_end(base); in sdhi_boot_request()
220 cmd->resp[0] = sd_ctrl_read32(base, CTL_RESPONSE); in sdhi_boot_request()
225 static int sdhi_boot_do_read_single(void __iomem *base, int high_capacity, in sdhi_boot_do_read_single() argument
241 err = sdhi_boot_request(base, &cmd); in sdhi_boot_do_read_single()
246 sd_ctrl_write32(base, CTL_IRQ_MASK, in sdhi_boot_do_read_single()
249 sd_ctrl_read32(base, CTL_IRQ_MASK)); in sdhi_boot_do_read_single()
250 err = sdhi_boot_wait_resp_end(base); in sdhi_boot_do_read_single()
254 sd_ctrl_write16(base, CTL_SD_XFER_LEN, TMIO_BBS); in sdhi_boot_do_read_single()
256 *buf++ = sd_ctrl_read16(base, RESP_CMD12); in sdhi_boot_do_read_single()
258 err = sdhi_boot_wait_resp_end(base); in sdhi_boot_do_read_single()
265 int sdhi_boot_do_read(void __iomem *base, int high_capacity, in sdhi_boot_do_read() argument
273 err = sdhi_boot_do_read_single(base, high_capacity, offset + i, in sdhi_boot_do_read()
285 int sdhi_boot_init(void __iomem *base) in sdhi_boot_init() argument
291 sdhi_boot_mmc_clk_stop(base); in sdhi_boot_init()
292 sdhi_boot_reset(base); in sdhi_boot_init()
300 err = sdhi_boot_mmc_set_ios(base, &ios); in sdhi_boot_init()
312 err = sdhi_boot_request(base, &cmd); in sdhi_boot_init()
324 err = sdhi_boot_request(base, &cmd); /* Ignore error */ in sdhi_boot_init()
340 err = sdhi_boot_request(base, &cmd); in sdhi_boot_init()
350 err = sdhi_boot_request(base, &cmd); in sdhi_boot_init()
373 err = sdhi_boot_request(base, &cmd); in sdhi_boot_init()
392 err = sdhi_boot_request(base, &cmd); in sdhi_boot_init()
407 err = sdhi_boot_request(base, &cmd); in sdhi_boot_init()
419 err = sdhi_boot_request(base, &cmd); in sdhi_boot_init()
432 err = sdhi_boot_request(base, &cmd); in sdhi_boot_init()
443 err = sdhi_boot_request(base, &cmd); in sdhi_boot_init()