26 #define DMA_CCR(chan)		(chan->mmr_base + 0x0)  argument
27 #define DMA_CSR(chan)		(chan->mmr_base + 0x4)  argument
28 #define DMA_DAR(chan)		(chan->mmr_base + 0xc)  argument
29 #define DMA_NDAR(chan)		(chan->mmr_base + 0x10)  argument
30 #define DMA_PADR(chan)		(chan->mmr_base + 0x14)  argument
31 #define DMA_PUADR(chan)	(chan->mmr_base + 0x18)  argument
32 #define DMA_LADR(chan)		(chan->mmr_base + 0x1c)  argument
33 #define DMA_BCR(chan)		(chan->mmr_base + 0x20)  argument
34 #define DMA_DCR(chan)		(chan->mmr_base + 0x24)  argument
37 #define AAU_ACR(chan)		(chan->mmr_base + 0x0)  argument
38 #define AAU_ASR(chan)		(chan->mmr_base + 0x4)  argument
39 #define AAU_ADAR(chan)		(chan->mmr_base + 0x8)  argument
40 #define AAU_ANDAR(chan)	(chan->mmr_base + 0xc)  argument
41 #define AAU_SAR(src, chan)	(chan->mmr_base + (0x10 + ((src) << 2)))  argument
42 #define AAU_DAR(chan)		(chan->mmr_base + 0x20)  argument
43 #define AAU_ABCR(chan)		(chan->mmr_base + 0x24)  argument
44 #define AAU_ADCR(chan)		(chan->mmr_base + 0x28)  argument
45 #define AAU_SAR_EDCR(src_edc)	(chan->mmr_base + (0x02c + ((src_edc-4) << 2)))
258 static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan)  in iop_chan_get_current_descriptor()  argument
260 	int id = chan->device->id;  in iop_chan_get_current_descriptor()
265 		return __raw_readl(DMA_DAR(chan));  in iop_chan_get_current_descriptor()
267 		return __raw_readl(AAU_ADAR(chan));  in iop_chan_get_current_descriptor()
274 static inline void iop_chan_set_next_descriptor(struct iop_adma_chan *chan,  in iop_chan_set_next_descriptor()  argument
277 	int id = chan->device->id;  in iop_chan_set_next_descriptor()
282 		__raw_writel(next_desc_addr, DMA_NDAR(chan));  in iop_chan_set_next_descriptor()
285 		__raw_writel(next_desc_addr, AAU_ANDAR(chan));  in iop_chan_set_next_descriptor()
296 static inline int iop_chan_is_busy(struct iop_adma_chan *chan)  in iop_chan_is_busy()  argument
298 	u32 status = __raw_readl(DMA_CSR(chan));  in iop_chan_is_busy()
341 iop_chan_interrupt_slot_count(int *slots_per_op, struct iop_adma_chan *chan)  in iop_chan_interrupt_slot_count()  argument
343 	switch (chan->device->id) {  in iop_chan_interrupt_slot_count()
402 					struct iop_adma_chan *chan)  in iop_desc_get_dest_addr()  argument
406 	switch (chan->device->id) {  in iop_desc_get_dest_addr()
420 					  struct iop_adma_chan *chan)  in iop_desc_get_qdest_addr()  argument
427 					struct iop_adma_chan *chan)  in iop_desc_get_byte_count()  argument
431 	switch (chan->device->id) {  in iop_desc_get_byte_count()
460 					struct iop_adma_chan *chan,  in iop_desc_get_src_addr()  argument
465 	switch (chan->device->id) {  in iop_desc_get_src_addr()
677 					struct iop_adma_chan *chan,  in iop_desc_set_byte_count()  argument
682 	switch (chan->device->id) {  in iop_desc_set_byte_count()
697 			struct iop_adma_chan *chan)  in iop_desc_init_interrupt()  argument
701 	switch (chan->device->id) {  in iop_desc_init_interrupt()
744 					struct iop_adma_chan *chan,  in iop_desc_set_dest_addr()  argument
749 	switch (chan->device->id) {  in iop_desc_set_dest_addr()
841 static inline void iop_chan_append(struct iop_adma_chan *chan)  in iop_chan_append()  argument
845 	dma_chan_ctrl = __raw_readl(DMA_CCR(chan));  in iop_chan_append()
847 	__raw_writel(dma_chan_ctrl, DMA_CCR(chan));  in iop_chan_append()
850 static inline u32 iop_chan_get_status(struct iop_adma_chan *chan)  in iop_chan_get_status()  argument
852 	return __raw_readl(DMA_CSR(chan));  in iop_chan_get_status()
855 static inline void iop_chan_disable(struct iop_adma_chan *chan)  in iop_chan_disable()  argument
857 	u32 dma_chan_ctrl = __raw_readl(DMA_CCR(chan));  in iop_chan_disable()
859 	__raw_writel(dma_chan_ctrl, DMA_CCR(chan));  in iop_chan_disable()
862 static inline void iop_chan_enable(struct iop_adma_chan *chan)  in iop_chan_enable()  argument
864 	u32 dma_chan_ctrl = __raw_readl(DMA_CCR(chan));  in iop_chan_enable()
867 	__raw_writel(dma_chan_ctrl, DMA_CCR(chan));  in iop_chan_enable()
870 static inline void iop_adma_device_clear_eot_status(struct iop_adma_chan *chan)  in iop_adma_device_clear_eot_status()  argument
872 	u32 status = __raw_readl(DMA_CSR(chan));  in iop_adma_device_clear_eot_status()
874 	__raw_writel(status, DMA_CSR(chan));  in iop_adma_device_clear_eot_status()
877 static inline void iop_adma_device_clear_eoc_status(struct iop_adma_chan *chan)  in iop_adma_device_clear_eoc_status()  argument
879 	u32 status = __raw_readl(DMA_CSR(chan));  in iop_adma_device_clear_eoc_status()
881 	__raw_writel(status, DMA_CSR(chan));  in iop_adma_device_clear_eoc_status()
884 static inline void iop_adma_device_clear_err_status(struct iop_adma_chan *chan)  in iop_adma_device_clear_err_status()  argument
886 	u32 status = __raw_readl(DMA_CSR(chan));  in iop_adma_device_clear_err_status()
888 	switch (chan->device->id) {  in iop_adma_device_clear_err_status()
900 	__raw_writel(status, DMA_CSR(chan));  in iop_adma_device_clear_err_status()
904 iop_is_err_int_parity(unsigned long status, struct iop_adma_chan *chan)  in iop_is_err_int_parity()  argument
910 iop_is_err_mcu_abort(unsigned long status, struct iop_adma_chan *chan)  in iop_is_err_mcu_abort()  argument
916 iop_is_err_int_tabort(unsigned long status, struct iop_adma_chan *chan)  in iop_is_err_int_tabort()  argument
922 iop_is_err_int_mabort(unsigned long status, struct iop_adma_chan *chan)  in iop_is_err_int_mabort()  argument
928 iop_is_err_pci_tabort(unsigned long status, struct iop_adma_chan *chan)  in iop_is_err_pci_tabort()  argument
930 	switch (chan->device->id) {  in iop_is_err_pci_tabort()
940 iop_is_err_pci_mabort(unsigned long status, struct iop_adma_chan *chan)  in iop_is_err_pci_mabort()  argument
942 	switch (chan->device->id) {  in iop_is_err_pci_mabort()
952 iop_is_err_split_tx(unsigned long status, struct iop_adma_chan *chan)  in iop_is_err_split_tx()  argument
954 	switch (chan->device->id) {  in iop_is_err_split_tx()