467 	val = readl_relaxed(reg);  in pll_enable()
476 	while (!(readl_relaxed(reg) & BM_PLL_LOCK) && --timeout)  in pll_enable()
483 	val = readl_relaxed(reg);  in pll_enable()
496 	val = readl_relaxed(reg);  in pll_disable()
507 	u32 div = (readl_relaxed(PLL1_SYS) & BM_PLL_SYS_DIV_SELECT) >>  in pll1_sys_get_rate()
521 	val = readl_relaxed(PLL1_SYS);  in pll1_sys_set_rate()
531 	u32 div = (readl_relaxed(PLL8_ENET) & BM_PLL_ENET_DIV_SELECT) >>  in pll8_enet_get_rate()
569 	val = readl_relaxed(PLL8_ENET);  in pll8_enet_set_rate()
581 	u32 mfn = readl_relaxed(reg + PLL_NUM_OFFSET);  in pll_av_get_rate()
582 	u32 mfd = readl_relaxed(reg + PLL_DENOM_OFFSET);  in pll_av_get_rate()
583 	u32 div = (readl_relaxed(reg) & BM_PLL_AV_DIV_SELECT) >>  in pll_av_get_rate()
606 	val = readl_relaxed(reg);  in pll_av_set_rate()
645 	div = (readl_relaxed(reg) & bm) >> bp;  in pll_get_rate()
664 	val = readl_relaxed(reg);  in pll_set_rate()
712 	frac = readl_relaxed(clk->enable_reg) >> bp_frac & PFD_FRAC_MASK;  in pfd_get_rate()
741 	val = readl_relaxed(clk->enable_reg);  in pfd_set_rate()
779 	val = readl_relaxed(clk->enable_reg);  in pfd_enable()
796 	val = readl_relaxed(clk->enable_reg);  in pfd_disable()
876 	u32 val = readl_relaxed(CCSR);  in pll1_sw_clk_set_parent()
933 	reg = readl_relaxed(clk->enable_reg);  in _clk_enable()
943 	reg = readl_relaxed(clk->enable_reg);  in _clk_disable()
951 	reg = readl_relaxed(clk->enable_reg);  in _clk_enable_1b()
961 	reg = readl_relaxed(clk->enable_reg);  in _clk_disable_1b()
1072 	u32 val = readl_relaxed(CSCMR2);  in ldb_di_clk_get_rate()
1085 	u32 val = readl_relaxed(CSCMR2);  in ldb_di_clk_set_rate()
1125 	val = readl_relaxed(d->reg);  in _clk_get_rate()
1150 	while ((readl_relaxed(CDHIPR) & bm) && --timeout)  in clk_busy_wait()
1195 	val = readl_relaxed(d->reg);  in _clk_set_rate()
1750 	val = readl_relaxed(m->reg);  in _clk_set_parent()
1888 	val = readl_relaxed(PLL8_ENET);  in pcie_clk_enable()
1901 	val = readl_relaxed(PLL8_ENET);  in pcie_clk_disable()
1920 	val = readl_relaxed(PLL8_ENET);  in sata_clk_enable()
1933 	val = readl_relaxed(PLL8_ENET);  in sata_clk_disable()
1999 	u32 val = readl_relaxed(CLPCR);  in imx6q_set_lpm()