Lines Matching refs:MX51_GPC_BASE
19 #define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR) macro
505 #define MXC_DPTC_LP_BASE (MX51_GPC_BASE + 0x80)
506 #define MXC_DPTC_GP_BASE (MX51_GPC_BASE + 0x100)
507 #define MXC_DVFS_CORE_BASE (MX51_GPC_BASE + 0x180)
508 #define MXC_DPTC_PER_BASE (MX51_GPC_BASE + 0x1C0)
509 #define MXC_PGC_IPU_BASE (MX51_GPC_BASE + 0x220)
510 #define MXC_PGC_VPU_BASE (MX51_GPC_BASE + 0x240)
511 #define MXC_PGC_GPU_BASE (MX51_GPC_BASE + 0x260)
512 #define MXC_SRPG_NEON_BASE (MX51_GPC_BASE + 0x280)
513 #define MXC_SRPG_ARM_BASE (MX51_GPC_BASE + 0x2A0)
514 #define MXC_SRPG_EMPGC0_BASE (MX51_GPC_BASE + 0x2C0)
515 #define MXC_SRPG_EMPGC1_BASE (MX51_GPC_BASE + 0x2D0)
516 #define MXC_SRPG_MEGAMIX_BASE (MX51_GPC_BASE + 0x2E0)
517 #define MXC_SRPG_EMI_BASE (MX51_GPC_BASE + 0x300)
550 #define MXC_GPC_CNTR (MX51_GPC_BASE + 0x0)
551 #define MXC_GPC_PGR (MX51_GPC_BASE + 0x4)
552 #define MXC_GPC_VCR (MX51_GPC_BASE + 0x8)
553 #define MXC_GPC_ALL_PU (MX51_GPC_BASE + 0xC)
554 #define MXC_GPC_NEON (MX51_GPC_BASE + 0x10)