Lines Matching refs:div4_clks
230 struct clk div4_clks[DIV4_NR] = { variable
267 [MSTP117] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
270 [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
304 CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
305 CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
306 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
307 CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
308 CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
309 CLKDEV_CON_ID("hpp_clk", &div4_clks[DIV4_HPP]),
310 CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]),
311 CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
312 CLKDEV_CON_ID("m3_clk", &div4_clks[DIV4_M3]),
313 CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
368 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); in r8a7740_clock_init()