Lines Matching refs:div4_clks
74 static struct clk div4_clks[DIV4_NR] = { variable
94 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */
95 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */
96 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */
97 [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0), /* SCIF3 */
98 [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0), /* SCIF4 */
99 [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), /* SCIF5 */
100 [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), /* TMU0 */
101 [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), /* TMU1 */
102 [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), /* TMU2 */
116 .parent = &div4_clks[DIV4_S],
121 .parent = &div4_clks[DIV4_S],
136 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_S]),
137 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_OUT]),
138 CLKDEV_CON_ID("shyway4_clk", &div4_clks[DIV4_S4]),
139 CLKDEV_CON_ID("shyway3_clk", &div4_clks[DIV4_S3]),
140 CLKDEV_CON_ID("shyway1_clk", &div4_clks[DIV4_S1]),
141 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
162 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); in r8a7779_clock_init()