Lines Matching refs:div4_clks
352 static struct clk div4_clks[DIV4_NR] = { variable
525 [MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */
526 [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
527 [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
528 [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */
529 [MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU */
530 [MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2 */
532 [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */
533 [MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
536 [MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */
537 [MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */
538 [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
540 [MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */
541 [MSTP217] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */
542 [MSTP216] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 16, 0), /* DMAC3 */
543 [MSTP214] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 14, 0), /* USBDMAC */
556 [MSTP315] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 15, 0), /* FLCTL*/
557 [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
558 [MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
559 [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */
560 [MSTP423] = MSTP(&div4_clks[DIV4_B], SMSTPCR4, 23, 0), /* DSITX1 */
561 [MSTP415] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */
565 [MSTP407] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 7, 0), /* USB-DMAC1 */
588 CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
589 CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
590 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
591 CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
592 CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]),
593 CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]),
594 CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
595 CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
596 CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
597 CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]),
598 CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]),
599 CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
600 CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
601 CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
602 CLKDEV_CON_ID("ddrp_clk", &div4_clks[DIV4_DDRP]),
698 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); in sh7372_clock_init()