Lines Matching refs:reg_shift
457 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON; in tegra2_bus_clk_init()
458 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1; in tegra2_bus_clk_init()
470 val &= ~(BUS_CLK_DISABLE << c->reg_shift); in tegra2_bus_clk_enable()
486 val |= BUS_CLK_DISABLE << c->reg_shift; in tegra2_bus_clk_disable()
505 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift); in tegra2_bus_clk_set_rate()
506 val |= (i - 1) << c->reg_shift; in tegra2_bus_clk_set_rate()
764 val >>= c->reg_shift; in tegra2_pll_div_clk_init()
792 new_val = val >> c->reg_shift; in tegra2_pll_div_clk_enable()
797 val &= ~(0xFFFF << c->reg_shift); in tegra2_pll_div_clk_enable()
798 val |= new_val << c->reg_shift; in tegra2_pll_div_clk_enable()
824 new_val = val >> c->reg_shift; in tegra2_pll_div_clk_disable()
829 val &= ~(0xFFFF << c->reg_shift); in tegra2_pll_div_clk_disable()
830 val |= new_val << c->reg_shift; in tegra2_pll_div_clk_disable()
857 new_val = val >> c->reg_shift; in tegra2_pll_div_clk_set_rate()
864 val &= ~(0xFFFF << c->reg_shift); in tegra2_pll_div_clk_set_rate()
865 val |= new_val << c->reg_shift; in tegra2_pll_div_clk_set_rate()
1484 .reg_shift = 28,
1517 .reg_shift = 0,
1558 .reg_shift = 0,
1599 .reg_shift = 0,
1609 .reg_shift = 16,
1619 .reg_shift = 0,
1629 .reg_shift = 16,
1665 .reg_shift = 0,
1831 .reg_shift = 12,
1894 .reg_shift = 8,
1997 .reg_shift = 4,
2007 .reg_shift = 0,