Lines Matching refs:inputs
599 for (sel = c->inputs; sel->input != NULL; sel++) { in tegra30_super_clk_init()
641 for (sel = c->inputs; sel->input != NULL; sel++) { in tegra30_super_clk_set_parent()
1432 for (sel = c->inputs; sel->input != NULL; sel++) { in tegra30_periph_clk_init()
1441 c->parent = c->inputs[0].input; in tegra30_periph_clk_init()
1549 for (sel = c->inputs; sel->input != NULL; sel++) { in tegra30_periph_clk_set_parent()
1734 for (sel = c->inputs; sel->input != NULL; sel++) { in tegra30_dsib_clk_set_parent()
1785 for (sel = c->inputs; sel->input != NULL; sel++) { in tegra30_clk_out_init()
1832 for (sel = c->inputs; sel->input != NULL; sel++) { in tegra30_clk_out_set_parent()
1918 for (sel = c->inputs; sel->input != NULL; sel++) in tegra30_audio_sync_clk_init()
1942 for (sel = c->inputs; sel->input != NULL; sel++) { in tegra30_audio_sync_clk_set_parent()
2546 .inputs = mux_audio_sync_clk, \
2625 .inputs = mux_clkm_clkm2_clkm4_extern##_id, \
2671 .inputs = mux_sclk,
2808 .inputs = mux_cclk_g,
2832 .inputs = _inputs, \
2850 .inputs = _inputs, \